Patents by Inventor Churamani GAIRE
Churamani GAIRE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180130656Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.Type: ApplicationFiled: December 15, 2017Publication date: May 10, 2018Inventors: Judson Robert Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James Mcardle, Murat Kerem Akarvardar
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Patent number: 9882052Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.Type: GrantFiled: June 30, 2016Date of Patent: January 30, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Robert Judson Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James McArdle, Murat Kerem Akarvardar
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Publication number: 20180006155Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Robert Judson HOLT, Jinping LIU, Jody FRONHEISER, Bharat KRISHNAN, Churamani GAIRE, Timothy James MCARDLE, Murat Kerem AKARVARDAR
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Patent number: 9349864Abstract: Methods for fabricating integrated circuits including selectively forming layers of increased dopant concentration are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a material layer with a selected facet on a selected plane and a non-selected facet on a non-selected plane. The method further includes performing an epitaxial deposition process with a dopant source to grow an in-situ doped epitaxial material on the material layer. The epitaxial deposition process grows the in-situ doped epitaxial material on the selected facet at a first growth rate and over the non-selected facet at a second growth rate greater than the first growth rate. A layer of increased dopant concentration is selectively formed over the selected facet.Type: GrantFiled: August 14, 2015Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Timothy James Mcardle, Judson Robert Holt, Churamani Gaire
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Publication number: 20150333067Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: ApplicationFiled: July 29, 2015Publication date: November 19, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE
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Patent number: 9147696Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: GrantFiled: October 1, 2013Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Jing Wan, Andy Wei, Lun Zhao, Dae Geun Yang, Jin Ping Liu, Tien-Ying Luo, Guillaume Bouche, Mariappan Hariharaputhiran, Churamani Gaire
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Publication number: 20150255353Abstract: Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops.Type: ApplicationFiled: March 5, 2014Publication date: September 10, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing WAN, Andy WEI, Jinping LIU, Xiang HU, Dae-han CHOI, Dae Geun YANG, Churamani GAIRE, Akshey SEHGAL
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Publication number: 20150214345Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.Type: ApplicationFiled: January 27, 2014Publication date: July 30, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing Wan, Jinping Liu, Churamani Gaire, Mariappan Hariharaputhiran, Andy Chih-Hung Wei, Bharat V. Krishnan, Cuiqin Xu, Michael Ganz
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Publication number: 20150194307Abstract: Methods for fabricating a strained fin structure are provided which include: providing a virtual substrate material over a substrate structure, the virtual substrate material having a virtual substrate lattice constant and a virtual substrate lattice structure; providing a first material over a region of the virtual substrate material, the first material acquiring a strained first material lattice structure by, in part, conforming to the virtual substrate lattice structure; and etching a first fin pattern into the first material. The method may include providing a second material over a second region of the virtual substrate material, the second material acquiring a strained lattice structure by, in part, conforming to the virtual substrate lattice structure, and etching a fin pattern into the second material. The resultant device may have tensile strained fin structures or compressively strained fin structures, or both.Type: ApplicationFiled: January 6, 2014Publication date: July 9, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Churamani GAIRE, Bharat KRISHNAN, Jin Ping LIU
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Publication number: 20150091094Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: ApplicationFiled: October 1, 2013Publication date: April 2, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE