Patents by Inventor Chuying Mao

Chuying Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11108372
    Abstract: An apparatus comprises a first circuit and a second circuit. The first circuit generally comprises differential symmetric band extension circuitry. The second circuit generally comprises coupled inductor coils configured to convert between differential and single-ended signal formats.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 31, 2021
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuying Mao, Ran Li
  • Publication number: 20210135647
    Abstract: An apparatus comprises a first circuit and a second circuit. The first circuit generally comprises differential symmetric band extension circuitry. The second circuit generally comprises coupled inductor coils configured to convert between differential and single-ended signal formats.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Inventors: Chuying Mao, Ran Li
  • Publication number: 20190372823
    Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: Chuying MAO, Ran LI, Jean-Marc MOURANT
  • Patent number: 10389572
    Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: August 20, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuying Mao, Ran Li, Jean-Marc Mourant
  • Publication number: 20180375711
    Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Inventors: CHUYING MAO, Ran LI, Jean-Marc MOURANT
  • Patent number: 10103690
    Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 16, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Naveen Yanduru, Chris Stephens, Jean-Marc Mourant, Chuying Mao
  • Publication number: 20180026583
    Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.
    Type: Application
    Filed: July 25, 2016
    Publication date: January 25, 2018
    Inventors: Naveen Yanduru, Chris Stephens, Jean-Marc Mourant, Chuying Mao
  • Patent number: 8604879
    Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 10, 2013
    Assignee: Integrated Device Technology Inc.
    Inventors: Jean-Marc Mourant, Feng-Jung Huang, Ran Li, Chuying Mao
  • Publication number: 20130257537
    Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Jean-Marc Mourant, Feng-Jung Huang, Ran Li, Chuying Mao