Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: Some embodiments relate to a method for forming a vertical cavity surface emitting laser (VCSEL) structure. The method includes forming an optically active layer over a lower reflective layer and forming an upper reflector over the optically active layer. A first spacer is formed along sidewalls of the upper reflector. An oxidation process is performed with the first spacer in place to oxidize a peripheral region of the optically active layer. A first etch process is performed on the lower reflective layer and the oxidized peripheral region, thereby forming a lower reflector and an optically active region.

Abstract: A semiconductor structure includes a substrate, an isolation structure disposed in the substrate, and a hybrid structure disposed over the isolation structure. The hybrid structure is substantially conformal with respect to a profile of the isolation structure. The hybrid structure includes an oxide component, a nitride component surrounding the oxide component, and a first polysilicon component alongside the nitride component. The nitride component includes a first upper surface closed to the first polysilicon component, and a second upper surface distal to the first polysilicon component. The second upper surface is lower than the first upper surface.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a piezoelectric membrane overlying a substrate. A plurality of conductive layers is disposed within the piezoelectric membrane. The plurality of conductive layers comprises a first conductive layer over a second conductive layer. The first conductive layer comprises a first electrode and the second conductive layer comprises a second electrode. A first conductive via is disposed in the piezoelectric membrane and contacts the first electrode. A second conductive via is disposed in the piezoelectric membrane and contacts the second electrode. A sidewall of the second conductive via comprises a vertical sidewall segment overlying a slanted sidewall segment.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate, and a drain region disposed within the substrate and separated from the source region. A plurality of separate isolation structures are disposed within the substrate. The plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another. A gate electrode is disposed within the substrate. The gate electrode includes a base region disposed between the source region and the plurality of separate isolation structures and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of separate isolation structures.

Abstract: The present disclosure provides a molecular marker for identifying fruiting characteristics of hermaphroditic papayas, wherein the molecular marker is selected from any of the nucleotide sequence group of SEQ ID NO: 1 to 11. This present disclosure also provides a method of using molecular markers for identifying fruiting characteristics of hermaphroditic papaya.

Abstract: An isolated nucleic acid includes a sequence selected from the group consisting of the following: (i) a first nucleotide sequence of SEQ ID NO.: 7, SEQ ID NO.: 3, SEQ ID NO.: 9, or SEQ ID NO.: 5; (ii) a second nucleotide sequence encoding the amino acid sequence of SEQ ID NO.: 6, SEQ ID NO.: 4, SEQ ID NO.: 8, or SEQ ID NO.: 10; and (iii) a third nucleotide sequence complementary to the first nucleotide sequence or the second nucleotide sequence.

Abstract: An isolated nucleic acid includes a sequence selected from the group consisting of the following: (i) a first nucleotide sequence of SEQ ID NO.: 1, SEQ ID NO.: 2, SEQ ID NO.: 3, SEQ ID NO.: 4, or SEQ ID NO.: 5; (ii) a second nucleotide sequence encoding an amino acid sequence of SEQ ID NO.: 6, SEQ ID NO.: 7, SEQ ID NO.: 8, SEQ ID NO.: 9, or SEQ ID NO.: 10; and (iii) a third nucleotide sequence complementary to the first nucleotide sequence or the second nucleotide sequence.

Abstract: A security system for code dump protection includes a storage device, a processor, and a decryption unit. The storage device has a protected storage area storing at least an encrypted code segment. The processor is utilized for issuing at least one address pattern to the storage device for obtaining at least one information pattern corresponding to the address pattern. The decryption unit checks the address pattern and the information pattern to generate a check result, and determines whether to decrypt the encrypted code segment in the protected storage area to generate a decrypted code segment to the processor according to the check result.

Abstract: A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.

Abstract: A buffer control system for generating a buffered signal having reduced buffer delay time between playback of tracks includes a controller module for providing an end target and for selection of a servo data signal corresponding to a desired track; a compare circuit coupled to the servo data signal for comparing a timestamp of the servo data signal to the end target, and asserting an end match signal when the timestamp of the servo data signal matches the end target; and a data buffering unit for storing the servo data signal as stored data to fill a capacity of an internal memory, and streaming out the buffered signal from the stored data in the internal memory when the capacity has reached a predetermined level; wherein the controller module is for updating selection of the servo data signal according to a next desired track upon assertion of the end match signal.

Abstract: The testing board is used to carry electrical device for electric testing. The testing board is constructed by a main testing board and a supporting board assembled on the lower surface of the main testing board. The main testing board and the supporting board respectively have a first thickness and a second thickness. The sum of the first thickness and the second thickness is matching the required distance of a testing apparatus.

Abstract: A method for controlling a storage system and the storage system using this method are disclosed. In the storage system, at least two memory units share an I/O bus. The shared I/O bus transfers information for each memory unit to execute an operation. The operation has at least one high priority cycle and at least one low priority cycle. When a low priority cycle is overlapped with a high priority cycle, the low priority cycle is suspended, and the high priority cycle is operated first. After the high priority cycle is finished, the suspended low priority cycle is then resumed. By doing so, the shared I/O bus may be used by one memory unit during a busy cycle for another memory unit, during which the latter memory unit does not use the I/O bus. Therefore, the I/O bus can be more efficiently used.

Abstract: A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.

Abstract: An electronic device having a stretchable USB receptacle is provided. An extending connecting cable is added to the USB receptacle on the electronic device. In normal condition, the connecting cable is accommodated in a cable reel to make the USB receptacle accommodated in an accommodating recess of the electronic device to keep consistency of the appearance. In using condition, the USB receptacle may be taken out and used in a needed place by drawing out the connecting cable. This overcomes the disadvantage that the conventional adjacent USB receptacles may be interfered with each other, and the scope of use also increases.

Abstract: The invention provides a multi-chip module. In one embodiment, the multi-chip module comprises a serial flash die and a primary die, and the primary die comprises a built-in self-test controller and a serial flash controller. The built-in self-test controller generates a write command to write first data to a memory location of the serial flash die, generates a read command to read second data from the memory location of the serial flash die, and compares the second data with the first data to determine whether the memory location is defective for generating failed address information about the serial flash die. The serial flash controller accesses the serial flash die according to the write command and the read command.

Abstract: An electronic device having a stretchable USB receptacle is provided. An extending connecting cable is added to the USB receptacle on the electronic device. In normal condition, the connecting cable is accommodated in a cable reel to make the USB receptacle accommodated in an accommodating recess of the electronic device to keep consistency of the appearance. In using condition, the USB receptacle may be taken out and used in a needed place by drawing out the connecting cable. This overcomes the disadvantage that the conventional adjacent USB receptacles may be interfered with each other, and the scope of use also increases.

Abstract: A security system for code dump protection includes a storage device, a processor, and a decryption unit. The storage device has a protected storage area storing at least an encrypted code segment. The processor is utilized for issuing at least one address pattern to the storage device for obtaining at least one information pattern corresponding to the address pattern. The decryption unit checks signal communicated between the processor and the storage device to generate a check result, and determines whether to decrypt the encrypted code segment in the protected storage area to generate a decrypted code segment to the processor according to the check result.

Abstract: A buffer control system for generating a buffered signal having reduced buffer delay time between playback of tracks includes a controller module for providing an end target and for selection of a servo data signal corresponding to a desired track; a compare circuit coupled to the servo data signal for comparing a timestamp of the servo data signal to the end target, and asserting an end match signal when the timestamp of the servo data signal matches the end target; and a data buffering unit for storing the servo data signal as stored data to fill a capacity of an internal memory, and streaming out the buffered signal from the stored data in the internal memory when the capacity has reached a predetermined level; wherein the controller module is for updating selection of the servo data signal according to a next desired track upon assertion of the end match signal.