Patents by Inventor Cian-Yu CHEN

Cian-Yu CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055496
    Abstract: A semiconductor structure includes a substrate, at least one gate electrode, a plurality of source/drain (S/D) regions, a backside contact, a first dielectric layer, and a conductive via. The at least one gate electrode is disposed in the substrate. The S/D regions is disposed in the substrate and laterally disposed aside the at least one gate electrode. The backside contact is disposed above the S/D regions and the at least one gate electrode. The first dielectric layer is disposed between the backside contact and the plurality of S/D regions and the at least one gate electrode. The conductive via is extended through the first dielectric layer to electrically connect the S/D regions and the backside contact. The conductive via includes an anisotropic transport material or a topological material.
    Type: Application
    Filed: August 14, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Pei Lu, Shin-Yi Yang, Yun-Chi Chiang, Han-Tang Hung, Cian-Yu Chen, Ming-Han Lee
  • Publication number: 20240055352
    Abstract: A semiconductor device includes a dielectric structure, a conductive structure disposed in the dielectric structure, a first dielectric feature disposed over the dielectric structure, a conductive element disposed in the first dielectric feature and connected to the conductive structure, and a barrier feature disposed around the conductive element and disposed outside of the conductive structure.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cian-Yu CHEN, Shin-Yi YANG, Ching-Fu YEH, Meng-Pei LU, Chin-Lung CHUNG, Yun-Chi CHIANG, Ming-Han LEE
  • Publication number: 20230352409
    Abstract: A semiconductor device includes a substrate and an interconnect layer disposed on the substrate. The interconnect layer includes a dielectric layer and an interconnect extending through the dielectric layer. The interconnect includes a bulk metal region and a single barrier/liner layer, which serves as both a barrier layer and a liner layer and which is disposed to separate the bulk metal region from the dielectric layer.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Pei LU, Shin-Yi YANG, Ching-Fu YEH, Chin-Lung CHUNG, Cian-Yu CHEN, Yun-Chi CHIANG, Tsu-Chun KUO, Ming-Han LEE
  • Publication number: 20230326857
    Abstract: A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Pei LU, Shin-Yi YANG, Cian-Yu CHEN, Yun-Chi CHIANG, Ming-Han LEE