Abstract: A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.

Abstract: An LLCC Secondary Overtone Resonant (LLCC-SOR) power converter obtains dramatically higher efficiency with light loads by providing a resonance in the transformer secondary that is approximately tuned to an odd order overtone of the upper primary switching frequency, an upper frequency limit of the primary switching frequency, and a secondary duty cycle control that engages once the upper primary switching frequency limit is reached. The transformer circuit resonates in an LLCC-SOR mode that regulates the output voltage when the maximum frequency limit is reached. In operation, the gain of the resonant circuit is raised above its regulation point under light loads, forcing the controller into duty cycle mode. The secondary current completes an odd number of oscillations per single oscillation of the primary current, and the primary current returns to near zero after each switching transition. Also, a zero-voltage switching condition is maintained on the primary switch.

Abstract: A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.

Abstract: An LLCC Secondary Overtone Resonant (LLCC-SOR) power converter obtains dramatically higher efficiency with light loads by providing a resonance in the transformer secondary that is approximately tuned to an odd order overtone of the upper primary switching frequency, an upper frequency limit of the primary switching frequency, and a secondary duty cycle control that engages once the upper primary switching frequency limit is reached. The transformer circuit resonates in an LLCC-SOR mode that regulates the output voltage when the maximum frequency limit is reached. In operation, the gain of the resonant circuit is raised above its regulation point under light loads, forcing the controller into duty cycle mode. The secondary current completes an odd number of oscillations per single oscillation of the primary current, and the primary current returns to near zero after each switching transition. Also, a zero-voltage switching condition is maintained on the primary switch.

Abstract: A Controller Area Network (CAN) driver (a transmitter) includes a conventional main driver having an open drain first driver MOSFET, for pulling up a first conductor of a bus in a dominant state, and an open drain second driver MOSFET, for pulling down a second conductor of the bus in the dominant state. Since it is difficult to perfectly match the driver MOSFET characteristics for conducting exactly equal currents during turning on and turning off, significant common mode fluctuations occur, resulting in electromagnetic emissions. Source followers are respectively connected in parallel with the first driver MOSFET and the second driver MOSFET for creating a low common mode loading impedance on the conductors during times when the main driver MOSFETs are turning on and turning off to greatly reduce any common mode fluctuations caused by the main driver MOSFETs.

Abstract: A Controller Area Network (CAN) driver (a transmitter) includes a conventional main driver having an open drain first driver MOSFET, for pulling up a first conductor of a bus in a dominant state, and an open drain second driver MOSFET, for pulling down a second conductor of the bus in the dominant state. Since it is difficult to perfectly match the driver MOSFET characteristics for conducting exactly equal currents during turning on and turning off, significant common mode fluctuations occur, resulting in electromagnetic emissions. Source followers are respectively connected in parallel with the first driver MOSFET and the second driver MOSFET for creating a low common mode loading impedance on the conductors during times when the main driver MOSFETs are turning on and turning off to greatly reduce any common mode fluctuations caused by the main driver MOSFETs.

Abstract: An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.

Abstract: A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is located. Next, an ESD protection device is placed at the center of gravity of the ESD-susceptible circuits located within the defined region. A determination is made as to whether or not all ESD-susceptible circuits within the list of ESD-susceptible circuits are protected by the placement of the ESD protection device. If so, the process is repeated in other regions until the entire integrated circuit is addressed. Otherwise, the defined region is divided into at least two smaller regions and the process is repeated.

Abstract: A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.