Abstract: A programmable method for analyzing the performance of software using a combination of statistical sampling, hardware events and feedback, and a finite state machine execution model. Performance analysis code is integrated with the object code of the software it is analyzing and profiling. Using hardware timers and triggers, the analysis code records timing information at each timer or trigger event, where some events may be the result of stochastic sampling. At certain times during the execution and termination of the software being profiled, results of the profiling are output. Upon the termination of the software being profiled, post processing is optionally performed on the profiling output timing information, and the result of this post processing provides a human readable indication of where the analyzed software spent its execution time. A system for implementing the profiling method in hardware is also described.

Abstract: A virtual memory image controller for multi-windowing, comprises a bidimensional image memory organized in N elementary blocks, N being an integer, the blocks being of fixed size and rectangular, a random access read/write memory containing a sequence of N pointers, each pointer noting the beginning address of a block in the image memory, a video signal generator delivering a video signal corresponding to the contents of n blocks of the image memory, NSN, for the display on a screen of the image composed of n blocks organized in amatrix, the blocks be ing addressed by the video generator via a table of indirection, an interface for read/write accesses to the image memory, the accesses being made via the indirection table, the controller comprising also a data bus, an address bus, a command bus, and a sequencer.

Abstract: A digital stroke generator reads and writes discrete stroke segments in a display memory. The generator comprises principally a line address register, a column address register, a command addresser, a counter and it may also include a data register. The command addresser which commands the incrementation and decrementation of the address registers comprises an octant register, a direction register in which the vector direction is memorized according to the ROTHMAN code and a transcoding matrix. The counter counts down the image points making up the vector to be drawn and blocks the processor when the count down is finished.

Abstract: A system for the management of the physical memory of a processor which utilizes a base register which is loaded, for each virtual address of the memory, by a base address of a discriptive register corresponding to a task to be performed by the processor. This system utilizes a descriptive register table, an adder receiving the binary value of the base address of the first descriptive register, and the binary value of the index corresponding to the first register. The outputs of the adder address one of the inputs of the descriptive register table, thus selecting a segment descriptive register corresponding to the task to be performed. Each of the descriptive registers of the table contains control bits sent to the processor which makes it possible for the processor to check whether, for the segment to which the processor must have access, the processor must operate in the local or overall mode and whether the processor must process an input-output operation or an access to the memory.