Patents by Inventor Ciby Thomas Thuruthiyil

Ciby Thomas Thuruthiyil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8309951
    Abstract: In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regions. The floating body test structure further includes a second gate and a first contact situated over the first source/drain region. A gate-to-channel current measured between the second gate and the first contact is utilized to determine the gate-to-body tunneling current. The gate-to-body tunneling current can be determined by subtracting the gate-to-channel current from twice a source/drain current of the floating body FET. The test structure may also include a second contact situated on a doped region in the semiconductor layer, where a diode current flow through the doped region determines a body voltage for the floating body FET.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: November 13, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sushant S. Suryagandh, Ciby Thomas Thuruthiyil
  • Patent number: 8064832
    Abstract: In one disclosed embodiment, the present method for determining a gate-to-body current for a floating body FET comprises measuring at least three unique gate-to-body currents corresponding to at least three unique body-tied FET structures, determining at least three unique relationships between the at least three unique gate-to-body currents and at least three gate-to-body current density components for the at least three unique body-tied FET structures, and utilizing those at least three unique relationships to determine the at least three gate-to-body current density components; wherein one of the gate-to-body current density components is used to determine the gate-to-body current for the floating body FET. In one embodiment, a test structure implements a method for determining a gate-to-body current in a floating body FET. The determined gate-to-body current may be used to predict hysteresis in the floating body FET.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: November 22, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sushant S. Suryagandh, Ciby Thomas Thuruthiyil
  • Publication number: 20090020754
    Abstract: In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regions. The floating body test structure further includes a second gate and a first contact situated over the first source/drain region. A gate-to-channel current measured between the second gate and the first contact is utilized to determine the gate-to-body tunneling current. The gate-to-body tunneling current can be determined by subtracting the gate-to-channel current from twice a source/drain current of the floating body FET. The test structure may also include a second contact situated on a doped region in the semiconductor layer, where a diode current flow through the doped region determines a body voltage for the floating body FET.
    Type: Application
    Filed: July 18, 2007
    Publication date: January 22, 2009
    Inventors: Sushant S. Suryagandh, Ciby Thomas Thuruthiyil
  • Publication number: 20090021280
    Abstract: In one disclosed embodiment, the present method for determining a gate-to-body current for a floating body FET comprises measuring at least three unique gate-to-body currents corresponding to at least three unique body-tied FET structures, determining at least three unique relationships between the at least three unique gate-to-body currents and at least three gate-to-body current density components for the at least three unique body-tied FET structures, and utilizing those at least three unique relationships to determine the at least three gate-to-body current density components; wherein one of the gate-to-body current density components is used to determine the gate-to-body current for the floating body FET. In one embodiment, a test structure implements a method for determining a gate-to-body current in a floating body FET. The determined gate-to-body current may be used to predict hysteresis in the floating body FET.
    Type: Application
    Filed: July 18, 2007
    Publication date: January 22, 2009
    Inventors: Sushant S. Suryagandh, Ciby Thomas Thuruthiyil
  • Patent number: 6849469
    Abstract: Real-time analysis and control of a semiconductor silicidation process. The architecture includes system and methods for monitor and control of a silicidation process during rapid thermal anneal. An FTIR system analyzes selected and/or random regions where silicidation is occurring, and signals the process control system to control the process according to the status of the analyzed silicide formations.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: February 1, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ciby Thomas Thuruthiyil, Bhanwar Singh, Ramkumar Subramanian