Abstract: Receivers and methods of testing are described. A receiver includes a plurality of receiver channels, each including an amplifier for receiving a signal from an antenna and a mixer downstream of the amplifier. A test signal generating circuit is configured to generate test signals. A signal path connects the test signal generating circuit and each receiver channel and couples to each receiver channel at a coupling between the amplifier and a mixer. A test signal from the test signal generating circuit is injectable to the parts of the receiver channel downstream of the amplifier. The test signal may alternatively be injected into the entire receiver channel. The receivers and methods may be used in wireless systems, such as radar systems and radio systems.

Abstract: Receivers and methods of testing are described. A receiver includes a plurality of receiver channels, each including an amplifier for receiving a signal from an antenna and a mixer downstream of the amplifier. A test signal generating circuit is configured to generate test signals. A signal path connects the test signal generating circuit and each receiver channel and couples to each receiver channel at a coupling between the amplifier and a mixer. A test signal from the test signal generating circuit is injectable to the parts of the receiver channel downstream of the amplifier. The test signal may alternatively be injected into the entire receiver channel. The receivers and methods may be used in wireless systems, such as radar systems and radio systems.

Abstract: A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).

Abstract: A head end (7) comprises a low noise converter (2) for providing signal bands including channels to one or more user units (3). The low noise converter is arranged as a low noise channel converter (2), which includes frequency multiplexing means (6) for multiplexing one or more user pre-selected channels to the user units (3). By effecting pre-selection in the low noise channel converter (2) the connection between the head end (7) and the user units (3) only contains a single communication medium (5), generally an already installed coaxial cable (5). Wanted channels for example for watching one television program and simultaneously recording another program are pre-selected and at the side of the low noise block put on the one cable.

Abstract: The invention relates to multi-band resonator circuits with inductors and capacitors. These resonator circuits are realized on integrated circuits. The inductors are realized according to the invention within one single coil comprising a center (2) tap and intermediate taps (4, 6).

Abstract: A tuner for receiving a satellite broadcast signal via an antenna means, said tuner being coupled to a control unit. The tuner is characterized in that it comprises a standard bilateral digital interface for transmitting a base-band signal obtained from the received signal received via the antenna means and for receiving control signals transmitted by the control unit, said signals being transmitted/received via a first bilateral bus.

Abstract: A tuning system (100) for receiving a radio frequency input signal included in a frequency range, the range having a maximum frequency and a minimum frequency and a plurality of non-overlapping bands, the tuning system (100) comprising a voltage-controlled oscillator (6) controlled by an analog signal (VT) and a first binary signal (D) and being characterized in that the analog signal (VT) is inputted to a window comparator (1), said comparator (1) having a low threshold (VL) which is indicative for the minimum frequency and a high threshold (VH) which is indicative for the maximum frequency.

Abstract: The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.