Abstract: An embodiment of the invention provides a liquid-level sensor to detect liquid-level information of a liquid to be tested in a container. The sensor includes an electrode, a sensing circuit, an amplifier and a controller. The electrode is disposed on the outer surface of the container, comprising a first electrode and a second electrode. The sensing circuit is coupled to a first electrode and a second electrode, and receives a clock signal to generate a first voltage signal and a second voltage signal. The amplifier receives the first voltage signal and the second voltage signal to output an output voltage. The controller acquires liquid-level information of the liquid to be tested according to the output voltage and a voltage-volume table.

Abstract: An embodiment of the invention provides a liquid-level sensor to detect liquid-level information of a liquid to be tested in a container. The sensor includes an electrode, a sensing circuit, an amplifier and a controller. The electrode is disposed on the outer surface of the container, comprising a first electrode and a second electrode. The sensing circuit is coupled to a first electrode and a second electrode, and receives a clock signal to generate a first voltage signal and a second voltage signal. The amplifier receives the first voltage signal and the second voltage signal to output an output voltage. The controller acquires liquid-level information of the liquid to be tested according to the output voltage and a voltage-volume table.

Abstract: An impedance analyzing device, adapted to a testee comprising an electrode or at least one battery cell, includes a signal capturing unit, a signal adjusting unit, a signal analyzing unit, a processing unit, and a power source supply unit providing a variable-frequency voltage signal to the testee. The signal adjusting unit receiving and adjusts a variable-frequency voltage signal and the current signal to generate an adjusted variable-frequency voltage signal and an adjusted current signal. The signal capturing unit captures a current signal generated by the testee in response to the variable-frequency voltage signal. The signal analyzing unit receives and analyzes the adjusted variable-frequency voltage signal and the adjusted current signal in frequency domain to obtain a frequency domain parameter and/or a time domain parameter. The processing unit receives the frequency domain parameter and/or the time domain parameter to obtain an impedance variation characteristic of the testee.

Abstract: An impedance analysis device adapted to an object under test (OUT) includes a signal generator, a signal analysis unit and a processing unit. The signal generator outputs a pulse signal to the OUT. The signal analysis unit acquires a response signal which the OUT responds to the pulse signal, and analyzes the response signal to obtain an analysis parameter. The processing unit coupled to the signal analysis unit receives the analysis parameter, so as to obtain an impedance variation characteristic of the OUT.

Abstract: An impedance analysis device adapted to an object under test (OUT) includes a signal generator, a signal analysis unit and a processing unit. The signal generator outputs a pulse signal to the OUT. The signal analysis unit acquires a response signal which the OUT responds to the pulse signal, and analyzes the response signal to obtain an analysis parameter. The processing unit coupled to the signal analysis unit receives the analysis parameter, so as to obtain an impedance variation characteristic of the OUT.

Abstract: An electrical stimulation apparatus and an electrical stimulation method are provided. The electrical stimulation apparatus may include an electrode unit, a measurement unit and a stimulation unit. The electrode unit is used for contacting a tissue of interest (target tissue). The measurement unit is coupled to the electrode unit. The measurement unit measure a tissue characteristic of the target tissue. The stimulation unit is coupled to the measurement unit and the electrode unit. The stimulation unit stimulates the target tissue through the electrode unit by using an electrical stimulation signal, and the stimulation unit determines an amount of charge of the electrical stimulation signal according to the tissue characteristic measured by the measurement unit.

Abstract: A tunable voltage-controlled pseudo-resistor structure, comprising: a symmetric PMOS transistor circuit and an auto-tuning circuit connected in series. Input of the auto-tuning circuit is connected to a central position Vf of the PMOS transistor circuit having its output Vg, with its purpose of keeping Vg?Vf at a constant value. The PMOS transistor circuit may produce body effect through various different bulk voltages. Through the auto-tuning circuit, Vg and Vf are kept constant to make current of transistor to produce compensation effect, such that regardless of Va>Vb or Va<Vb, a large resistance is maintained. Through utilizing the tunable voltage-controlled pseudo-resistor structure, constant resistance can be maintained under high input voltage, hereby reducing drifting of common-mode voltage, in achieving a superior resistance effect.

Abstract: An impedance analyzing device, adapted to a testee comprising an electrode or at least one battery cell, includes a signal capturing unit, a signal adjusting unit, a signal analyzing unit, a processing unit, and a power source supply unit providing a variable-frequency voltage signal to the testee. The signal adjusting unit receiving and adjusts a variable-frequency voltage signal and the current signal to generate an adjusted variable-frequency voltage signal and an adjusted current signal. The signal capturing unit captures a current signal generated by the testee in response to the variable-frequency voltage signal. The signal analyzing unit receives and analyzes the adjusted variable-frequency voltage signal and the adjusted current signal in frequency domain to obtain a frequency domain parameter and/or a time domain parameter. The processing unit receives the frequency domain parameter and/or the time domain parameter to obtain an impedance variation characteristic of the testee.

Abstract: A tunable voltage-controlled pseudo-resistor structure, comprising: a symmetric PMOS transistor circuit and an auto-tuning circuit connected in series. Input of the auto-tuning circuit is connected to a central position Vf of the PMOS transistor circuit having its output Vg, with its purpose of keeping Vg?Vf at a constant value. The PMOS transistor circuit may produce body effect through various different bulk voltages. Through the auto-tuning circuit, Vg and Vf are kept constant to make current of transistor to produce compensation effect, such that regardless of Va>Vb or Va<Vb, a large resistance is maintained. Through utilizing the tunable voltage-controlled pseudo-resistor structure, constant resistance can be maintained under high input voltage, hereby reducing drifting of common-mode voltage, in achieving a superior resistance effect.

Abstract: A SRAM architecture includes a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.

Abstract: A low complexity and low power phase shift keying demodulator structure includes a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler. The digitizer digitizes a BPSK signal for an output waveform. The phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal. The binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor. The sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only a small capacitance.

Abstract: A SRAM architecture comprises a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out stored in. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.

Abstract: A low complexity and low power phase shift keying demodulator structure comprises: a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler; wherein the digitizer digitizes a BPSK signal for an output waveform, the phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal, the binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor, the sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only small capacitance.

Abstract: A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.

Abstract: A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.