Abstract: A system and method for processing signals in a communication system is disclosed herein. The system and method comprises processing steps and processing logic for generating a downlink subframe comprising a preamble and a plurality of data bursts within a predetermined frequency band; embedding first and second sets of downlink subframe parameters in the downlink subframe; transmitting the downlink subframe; receiving the downlink subframe; processing data in the preamble to obtain channel quality indicator (CQI) information; and using the CQI information to select either the first set or set second set of downlink subframe parameters to process the data bursts in the downlink subframe.

Abstract: A system and method for processing signals in a communication system is disclosed herein. The system and method comprises processing steps and processing logic for generating a downlink subframe comprising a preamble and a plurality of data bursts within a predetermined frequency band; embedding first and second sets of downlink subframe parameters in the downlink subframe; transmitting the downlink subframe; receiving the downlink subframe; processing data in the preamble to obtain channel quality indicator (CQI) information; and using the CQI information to select either the first set or set second set of downlink subframe parameters to process the data bursts in the downlink subframe.

Abstract: A system and method for processing signals in a communication system is disclosed herein. The system and method comprises processing steps and processing logic for generating a downlink subframe comprising a preamble and a plurality of data bursts within a predetermined frequency band; embedding first and second sets of downlink subframe parameters in the downlink subframe; transmitting the downlink subframe; receiving the downlink subframe; processing data in the preamble to obtain channel quality indicator (CQI) information; and using the CQI information to select either the first set or set second set of downlink subframe parameters to process the data bursts in the downlink subframe.

Abstract: Methods and corresponding systems in a mobile station for switching communication networks include scheduling an alternate network period during a first communication session between a mobile station and a first network transceiver in a first network, wherein the first network uses a first protocol. During the alternate network period the mobile station searches for a transmission from a second network transceiver in a second network, wherein the second network uses a second protocol. A second communication session is requested between the mobile station and the second network transceiver. A second communication session is initiated between the mobile station and the second network transceiver.

Abstract: A system and method for processing signals in a communication system is disclosed herein. The system and method comprises processing steps and processing logic for generating a downlink subframe comprising a preamble and a plurality of data bursts within a predetermined frequency band; embedding first and second sets of downlink subframe parameters in the downlink subframe; transmitting the downlink subframe; receiving the downlink subframe; processing data in the preamble to obtain channel quality indicator (CQI) information; and using the CQI information to select either the first set or set second set of downlink subframe parameters to process the data bursts in the downlink subframe.

Abstract: A clock synthesizer for dividing a source clock by N.R including a logic circuit, a delay line, a select circuit, an accumulator, and a clock divider circuit. The logic circuit divides N.R by 2M to get NNEW.RNEW in which NNEW is zero and RNEW is at least 0.5. The delay line receives a first clock and has multiple delay taps, where the first clock is based on the source clock. The select circuit selects the delay taps based on a tap select value and provides a delayed clock. The accumulator adds RNEW for each cycle of the delayed clock and performs a modulo function on a sum value to generate the tap select value. The clock divider circuit transitions an output clock based on selected transitions of the delayed clock, which is achieved by dividing the first clock or the delayed clock by 2M?1.

Abstract: A method and apparatus for data logging at-speed March C+ memory Built-in Self-tests. The method of testing a memory includes providing the memory with a Test Control and Observe wrapper; enabling a Built-in Self-test mode operation; utilizing the Test Control and Observe wrapper to capture a memory output; and holding a memory data when a failure occurs. The apparatus includes a processing unit; a Built-in Self-test controller coupled to the processing unit; a data circuit coupled to the Built-in Self-test controller; an address circuit coupled to the Built-in Self-test controller; a control circuit coupled to the Built-in Self-test controller; a memory coupled to the data circuit, the address circuit and the control circuit; a comparator circuit coupled to the memory and to the Built-in Self-test controller; and a memory Test Control and Observe wrapper coupled to the memory.

Abstract: Systems and methods are described for a method and apparatus to data log at-speed March C+ memory Built-in Self-tests. A method of testing a memory includes providing the memory with a Test Control and Observe wrapper; enabling a Built-in Self-test mode operation; utilizing the Test Control and Observe wrapper to capture a memory output; and holding a memory data when a failure occurs. An apparatus includes a processing unit; a Built-in Self-test controller coupled to the processing unit; a data circuit coupled to the Built-in Self-test controller; an address circuit coupled to the Built-in Self-test controller; a control circuit coupled to the Built-in Self-test controller; a memory coupled to the data circuit, the address circuit and the control circuit; a comparator circuit coupled to the memory and to the Built-in Self-test controller; and a memory Test Control and Observe wrapper coupled to the memory.