Abstract: An initial clock gating function is introduced to an original circuit design. Using abstraction-refinement, the initial clock gating function is modified such that the gated circuit design is equivalent to the original circuit design. A model checker, such as a SAT solver, may be utilized to determine equivalency of two circuit designs. A counter-example may be determined by the model checker to negate equivalency. The counter-example may be utilized to modify the initial clock gating function to determine a modified gated circuit design that is equivalent to the original circuit design.

Abstract: An initial clock gating function is introduced to an original circuit design. Using abstraction-refinement, the initial clock gating function is modified such that the gated circuit design is equivalent to the original circuit design. A model checker, such as a SAT solver, may be utilized to determine equivalency of two circuit designs. A counter-example may be determined by the model checker to negate equivalency. The counter-example may be utilized to modify the initial clock gating function to determine a modified gated circuit design that is equivalent to the original circuit design.

Abstract: A method for verifying software source code that includes references to program variables includes processing the source code to derive a set of next-state functions representing control flow of the source code. The references to the program variables in the source code are replaced with non-deterministic choices in the next-state functions. The next-state functions including the non-deterministic choices are restricted to produce a finite-state model of the control flow. The finite-state model is then verified to find an error in the source code.

Abstract: A method for verifying software source code that includes references to program variables includes processing the source code to derive a set of next-state functions representing control flow of the source code. The references to the program variables in the source code are replaced with non-deterministic choices in the next-state functions. The next-state functions including the non-deterministic choices are restricted to produce a finite-state model of the control flow. The finite-state model is then verified to find an error in the source code.

Abstract: A computer-implemented method for systematically eliminating redundant circuit elements in a state machine of a model having sequential circuit elements possessing one of a fixed number of possible states, typically “0” and “1”. Initially, the sequential circuit elements are sorted into groups whose state is determinate i.e. equal to “0” or “1”. The state of each circuit element whose state is determinate is stored in memory and its next state is calculated and compared with its preceding state. Each circuit element whose successive states are different is moved to the group of indeterminate circuit elements, and the cycle is repeated in respect of all remaining determinate circuit elements until no further circuit elements are moved. Each of the remaining determinate circuit elements is then replaced by a constant equal to its corresponding state i.e. “0” or “1”.