Patents by Inventor Cindy Goldberg
Cindy Goldberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9002493Abstract: A semiconductor processing apparatus includes a semiconductor processing station for a semiconductor wafer, and an endpoint detector associated with the semiconductor processing station. The endpoint detector includes a non-contact probe configured to probe the semiconductor wafer, an optical transmitter configured to transmit an optical signal to the non-contact probe, and an optical receiver configured to receive a reflected optical signal from the non-contact probe. The controller controls the semiconductor processing station based on the reflected optical signal.Type: GrantFiled: February 21, 2012Date of Patent: April 7, 2015Assignee: STMicroelectronics, Inc.Inventors: John H. Zhang, Cindy Goldberg
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Patent number: 8987780Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.Type: GrantFiled: May 31, 2013Date of Patent: March 24, 2015Assignee: STMicroelectronics, Inc.Inventors: John H Zhang, Cindy Goldberg, Walter Kleemeier
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Publication number: 20140353722Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: John H. Zhang, Cindy Goldberg, Walter Kleemeier
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Patent number: 8900990Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.Type: GrantFiled: December 31, 2012Date of Patent: December 2, 2014Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Walter Kleemeier, Cindy Goldberg
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Publication number: 20140183735Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: John H. ZHANG, Lawrence A. Clevenger, Carl Radens, Yiheng XU, Walter Kleemeier, Cindy Goldberg
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Publication number: 20130218316Abstract: A semiconductor processing apparatus includes a semiconductor processing station for a semiconductor wafer, and an endpoint detector associated with the semiconductor processing station. The endpoint detector includes a non-contact probe configured to probe the semiconductor wafer, an optical transmitter configured to transmit an optical signal to the non-contact probe, and an optical receiver configured to receive a reflected optical signal from the non-contact probe. The controller controls the semiconductor processing station based on the reflected optical signal.Type: ApplicationFiled: February 21, 2012Publication date: August 22, 2013Applicant: STMicroelectronics, Inc.Inventors: John H. ZHANG, Cindy GOLDBERG
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Patent number: 8476765Abstract: A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure.Type: GrantFiled: December 6, 2010Date of Patent: July 2, 2013Assignee: STMicroelectronics, Inc.Inventors: John Hongguang Zhang, Cindy Goldberg, Walter Kleemeier, Ronald Kevin Sampson
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Publication number: 20120139114Abstract: A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure.Type: ApplicationFiled: December 6, 2010Publication date: June 7, 2012Applicant: STMicroelectronics, Inc.Inventors: John Hongguang Zhang, Cindy Goldberg, Walter Kleemeier, Ronald Kevin Sampson
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Publication number: 20120122373Abstract: A method and system for detecting and controller wafer surface pressure distribution. Detecting and controlling wafer surface pressure distribution comprises measuring in situ wafer uniformity of a wafer at a plurality of locations of the wafer; and in response to the measured wafer uniformity controlling through a feedback loop in situ CMP head pressure applied at the plurality of locations of the wafer in real time to polish the wafer.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: STMICROELECTRONICS, INC.Inventors: John H. Zhang, Paul Ferreira, Cindy Goldberg
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Patent number: 7994069Abstract: To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.Type: GrantFiled: March 31, 2005Date of Patent: August 9, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Brad Smith, Cindy Goldberg, Robert E. Jones
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Patent number: 7951729Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.Type: GrantFiled: February 12, 2010Date of Patent: May 31, 2011Assignee: NXP B.V.Inventors: Janos Farkas, Srdjan Kordic, Cindy Goldberg
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Patent number: 7691756Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.Type: GrantFiled: September 1, 2006Date of Patent: April 6, 2010Assignee: NXP B.V.Inventors: Janos Farkas, Srdjan Kordic, Cindy Goldberg
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Publication number: 20090301867Abstract: A system for processing a semiconductor substrate during fabrication of semiconductor devices provides a plurality of semiconductor substrate processing stations in a physically integrated system, as well as a semiconductor substrate transport system for transporting a semiconductor substrate between the respective processing stations. In particular, the processing system according to the present invention favors the use of liquid phase process steps, particularly deposition process steps, instead of gas or vapor phase processing. Even more particularly, the system contemplates deposition of a metallic barrier layer 30 on the semiconductor substrate in liquid phase.Type: ApplicationFiled: February 24, 2006Publication date: December 10, 2009Applicant: CITIBANK N.A.Inventors: Janos Farkas, Cindy Goldberg, Katie Yu, Srdjan Kordic
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Publication number: 20090134496Abstract: A wafer comprises a multi-layer structure. The multi-layer structure includes a first device structure neighbouring an area for receiving alignment markers. A plurality of alignment markers extend into the multi-layer structure and are located within the area for receiving alignment markers. The plurality of alignment markers is arranged to prevent propagation of a crack, when occurring, beyond a material-dependent critical length in a part of the multi-layer structure corresponding to the area for receiving the alignment structure. The material-dependent critical length is associated with the part of the multi-layer structure.Type: ApplicationFiled: July 6, 2006Publication date: May 28, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Scott Warrick, Clyde Browning, Kevin Cooper, Cindy Goldberg, Brad Smith
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Publication number: 20080182379Abstract: To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.Type: ApplicationFiled: March 31, 2005Publication date: July 31, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Brad Smith, Cindy Goldberg, Robert E. Jones