Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that plates on electrical current density modifier portions (364) of structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: An electroplating system (30) and process makes electrical current density across, a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).

Abstract: A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.

Abstract: A method is provided for selectively metallizing one or more three-dimensional materials in an electronic circuit package comprising the steps of forming a layer of seeding solution on a surface of the three-dimensional material of interest, exposing this layer to light of appropriate wavelength, resulting in the formation of metal seed on regions of the three-dimensional material corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper.

Abstract: In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).

Abstract: A method for selectively metallizing one or more through-holes, other openings (such as slots), or edges of an electronic circuit package comprising the steps of forming a layer of seeding solution on a drilled surface of a substrate of interest exposing this layer to light of appropriate wavelength, through a mask that does not completely cover the through-holes or openings and thereby results in the formation of metal seed on regions of the substrate surface corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper.

Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: A method for selectively metallizing one or more through-holes, other openings (such as slots), or edges of an electronic circuit package comprising the steps of forming a layer of seeding solution on a drilled surface of a substrate of interest exposing this layer to light of appropriate wavelength, through a mask that does not completely cover the through-holes or openings and thereby results in the formation of metal seed on regions of the substrate surface corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper.

Abstract: A method is provided for selectively metallizing one or more three-dimensional materials in an electronic circuit package comprising the steps of forming a layer of seeding solution on a surface of the three-dimensional material of interest, exposing this layer to light of appropriate wavelength, resulting in the formation of metal seed on regions of the three-dimensional material corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper.

Abstract: A method is provided for selectively metallizing one or more three-dimensional materials in an electronic circuit package comprising the steps of forming a layer of seeding solution on a surface of the three-dimensional material of interest, exposing this layer to light of appropriate wavelength, resulting in the formation of metal seed on regions of the three-dimensional material corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper.