Patents by Inventor Cing Gie Lim
Cing Gie Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11522131Abstract: An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.Type: GrantFiled: July 31, 2020Date of Patent: December 6, 2022Assignee: GLOBALFOUNDRIES SINGAPORE PTE LTDInventors: Curtis Chun-I Hsieh, Wanbing Yi, Benfu Lin, Cing Gie Lim, Wei-Hui Hsu, Juan Boon Tan
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Patent number: 11335635Abstract: A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.Type: GrantFiled: April 8, 2020Date of Patent: May 17, 2022Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Benfu Lin, Kah Wee Gan, Cing Gie Lim, Chengang Feng
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Publication number: 20220037590Abstract: An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.Type: ApplicationFiled: July 31, 2020Publication date: February 3, 2022Inventors: Curtis Chun-I Hsieh, Wanbing Yi, Benfu Lin, Cing Gie Lim, Wei-Hui Hsu, Juan Boon Tan
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Publication number: 20210320063Abstract: A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.Type: ApplicationFiled: April 8, 2020Publication date: October 14, 2021Inventors: BENFU LIN, KAH WEE GAN, CING GIE LIM, CHENGANG FENG
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Patent number: 10475990Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.Type: GrantFiled: January 22, 2018Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Curtis Chun-I Hsieh, Lup San Leong, Wanbing Yi, Cing Gie Lim, Yi Jiang, Juan Boon Tan
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Publication number: 20190229261Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.Type: ApplicationFiled: January 22, 2018Publication date: July 25, 2019Inventors: Curtis Chun-I HSIEH, Lup San LEONG, Wanbing YI, Cing Gie LIM, Yi JIANG, Juan Boon TAN
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Publication number: 20160114457Abstract: A polishing pad for use in chemical mechanical polishing of a substrate is disclosed. The polishing pad includes first and second major surfaces. The first major surface forms a polishing surface and is divided into a main portion and edge portions. The edge portions are nearer to edges of the polishing pad while the main portion is between the edge portions and farther from the edges of the polishing pad. The polishing pad also includes a plurality of polishing posts disposed on the first major surface of the pad. The densities of the polishing posts in the edge portions and main portion are different.Type: ApplicationFiled: October 24, 2014Publication date: April 28, 2016Inventors: Lup San LEONG, Cing Gie LIM, Wei LU, Ming ZENG, Alex SEE
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Patent number: 9076735Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process.Type: GrantFiled: November 27, 2013Date of Patent: July 7, 2015Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lup San Leong, Alan Cing Gie Lim, Ling Wu, Jian Bo Yang
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Publication number: 20150147872Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Inventors: Lup San Leong, Alan Cing Gie Lim, Ling Wu, Jian Bo Yang
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Publication number: 20090014883Abstract: An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region is formed between the first region and the second region. An opening is formed in the third region and a material is deposited within the opening for preventing erosion of the first region.Type: ApplicationFiled: September 23, 2008Publication date: January 15, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Dong Sheng Liu, Cing Gie Lim, Subbiah Chettiar Mahadevan, Feng Chen
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Patent number: 7446039Abstract: An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region is formed between the first region and the second region. An opening is formed in the third region and a material is deposited within the opening for preventing erosion of the first region.Type: GrantFiled: January 25, 2006Date of Patent: November 4, 2008Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Dong Sheng Liu, Cing Gie Lim, Subbiah Chettiar Mahadevan, Feng Chen
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Publication number: 20070173016Abstract: An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region is formed between the first region and the second region. An opening is formed in the third region and a material is deposited within the opening for preventing erosion of the first region.Type: ApplicationFiled: January 25, 2006Publication date: July 26, 2007Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Dong Sheng Liu, Cing Gie Lim, Subbiah Chettiar Mahadevan, Feng Chen