Abstract: Examples described herein provide for determining a recipe for identifying from which buckets integrated circuit chips are taken to form units of a multi-chip apparatus. In an example, a method uses a processor-based system and uses a Markov Decision Process. Buckets are defined based on respective characteristics of manufactured chips. Each of the manufactured chips is binned into a respective one of the buckets based on the characteristic of the respective manufactured chip. A recipe for identifying from which of the buckets to take one or more of the manufactured chips to incorporate into respective ones of the units of the multi-chip apparatus is generated.

Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Abstract: A method for tracking an interposer die of a stacked silicon interconnect technology (SSIT) product includes forming a plurality of dummy components on the interposer die, and modifying one or more of the plurality of dummy components on the interposer die to form a unique identifier for the interposer die. An apparatus for a stacked silicon interconnect technology (SSIT) product includes an interposer die, and a plurality of dummy components at the interposer die. One or more of the plurality of dummy components is modifiable to form a unique identifier for the interposer die.

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Abstract: An embodiment of an integrated circuit is disclosed. For this embodiment, the integrated circuit includes circuit blocks. At least one transistor of a circuit block of the circuit blocks includes a portion of a semiconductor substrate having a diffusion layer. The circuit block has a relatively high diffusion pattern density as compared with others of the circuit blocks. The diffusion layer has an exposed surface active area constrained responsive to a design rule. The design rule is to limit to a maximum amount the surface active area in order to improve at least one parameter of the at least one transistor selected from a group consisting of an increase in switching speed and a decrease in leakage current of the at least one transistor of the circuit block having the relatively high diffusion pattern density.

Abstract: A method of analyzing integrated circuit (IC) product yield can include storing, within a memory of a system comprising a processor, parametric data from a manufacturing process of an IC and determining a measure of non-random variation for at least one parameter of the parametric data using a pattern detection technique. The processor can compare the measure of non-random variation to a randomness criteria and selectively output a notification indicating that variation in the parameter is non-random according to the comparison of the measure of non-random variation to the randomness criteria.

Abstract: An embodiment of the present invention reduces resources needed to estimate the Icc Current Temperature Scaling Factor (ITSF) of a device, and provides a method and apparatus to estimate ITSF from the device speed and performance characteristics which can be measured at room temperature. In one embodiment, a method for estimating the ITSF of an integrated circuit includes: determining a level of propagation delay of a portion of the integrated circuit; and determining an estimated Icc current temperature scaling factor from a correlation between the level of the propagation delay and a modeled Icc current temperature scaling factor.

Abstract: According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

Abstract: A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer formed at or near an upper surface of the memory device and may be deposited at a relatively low temperature.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer which comprises silicon-rich TCS nitride. Further, an oxide cap layer is situated over the UV radiation blocking layer. The structure might further comprise an antireflective coating layer over the oxide cap layer. The interlayer dielectric may comprise BPSG and the oxide cap layer may comprise TEOS oxide.