Abstract: A computer-implemented method for designing an integrated circuit includes placing a predefined cell within a twin-well CMOS silicon-on-insulator integrated circuit design. The predefined cell comprises a logic region comprising one or more transistors of a first type, the first type being either conventional-well CMOS transistors or flipped-well CMOS transistors. The predefined cell also comprises an inner set of boundary cells that are arranged along one or more edges of the logic region, and an outer set of boundary cells that are arranged along one or more edges of the predefined cell and that are configured for placement adjacent transistors of a second type, the second type being either flipped-well CMOS transistors or conventional-well CMOS transistors and the second type being different from the first type.

Abstract: A method and system for generating multiple clock signals from a reference clock signal are provided. In one implementation, the system includes a reference clock to generate a reference clock signal having a first frequency, a first prescaler to receive the reference clock signal and generate a first output clock signal having a pre-determined frequency relative to the first frequency of the reference clock signal, and a second prescaler to receive the first output clock signal and generate a second output clock signal having a second pre-determined frequency relative to the first pre-determined frequency of the first output clock signal. The first output clock signal is substantially synchronous to the second output clock signal.

Abstract: A method and apparatus for testing correct operation of a page decoder in a memory is provided. In one implementation, the method includes erasing the memory to reset all memory cells associated with each of the N pages in the memory, and iteratively generating a unique bit sequence of M bits and programming the unique bit sequence into a plurality of the N pages at a given time until each of the N pages contains a unique bit sequence relative to other pages in the memory. Responsive to each of the N pages having a unique bit sequence, the method further includes using the page decoder to read out each unique bit sequence associated with the N pages to verify correct operation of the page decoder.

Abstract: A method and apparatus for testing correct operation of a page decoder in a memory is provided. In one implementation, the method includes erasing the memory to reset all memory cells associated with each of the N pages in the memory, and iteratively generating a unique bit sequence of M bits and programming the unique bit sequence into a plurality of the N pages at a given time until each of the N pages contains a unique bit sequence relative to other pages in the memory. Responsive to each of the N pages having a unique bit sequence, the method further includes using the page decoder to read out each unique bit sequence associated with the N pages to verify correct operation of the page decoder.

Abstract: A method and system for generating multiple clock signals from a reference clock signal are provided. In one implementation, the system includes a reference clock to generate a reference clock signal having a first frequency, a first prescaler to receive the reference clock signal and generate a first output clock signal having a pre-determined frequency relative to the first frequency of the reference clock signal, and a second prescaler to receive the first output clock signal and generate a second output clock signal having a second pre-determined frequency relative to the first pre-determined frequency of the first output clock signal. The first output clock signal is substantially synchronous to the second output clock signal.