Patents by Inventor Ciro Feliciano

Ciro Feliciano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168654
    Abstract: Methods, systems, and devices for data block refresh during read access are described. In some instances, when an access command (e.g., a read command) is received, a memory system may determine if the associated block is a PSA block. If the block is PSA block, its data may be provided to a host system to satisfy the read command and the block may either be refreshed or may be designated to be refreshed. For example, the block may be refreshed by copying its data to a write cache and writing the data from the cache to a new block. In other instances, an LBA of the block may be stored (e.g., designated) and the LBA may be refreshed when the memory system is idle.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 23, 2024
    Inventors: Luca Porzio, Ting Luo, Ciro Feliciano, Giuseppe D'Eliseo
  • Publication number: 20240029800
    Abstract: Methods, systems, and devices for threshold voltage scans are described. A memory device may receive a configuration for scanning a memory array during a scanning procedure. The memory device may read, during the scanning procedure, one or more memory cells of the memory array using a first voltage value that is indicated by the configuration. The memory device may store, during the scanning procedure, a first value in a first counter in response to reading the one or more memory cells of the memory array. The memory device may determine whether to terminate the scanning procedure in response to one or both of determining that the first quantity of memory cells satisfies a threshold quantity of memory cells or determining that the first voltage value satisfies a threshold voltage value to be scanned.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Inventors: Aniello Palomba, Ciro Feliciano, Antonio Imperiale
  • Publication number: 20230401007
    Abstract: Described are systems and methods for prioritization of background media management operations in memory systems. An example system comprises a controller coupled to a memory array comprising a plurality of memory cells. The controller is configured to perform operations, comprising: identifying a plurality of address ranges referencing respective sets of memory cells of the memory array, wherein each address range is associated with a respective memory access operation counter reflecting a number of memory access operations that have been performed with respect to a corresponding set of memory cells; identifying, among the plurality of address ranges, an address range associated with a maximum value of a corresponding memory access operation counter; and causing a media management operation to be performed with respect to a set of memory cells referenced by the identified address range.
    Type: Application
    Filed: May 18, 2023
    Publication date: December 14, 2023
    Inventors: Luca Porzio, Ciro Feliciano