Patents by Inventor Clément Gaumer

Clément Gaumer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9666679
    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: May 30, 2017
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Clement Gaumer, Daniel Benoit
  • Publication number: 20160343814
    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 24, 2016
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Clement Gaumer, Daniel Benoit
  • Patent number: 9437694
    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 6, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Clement Gaumer, Daniel Benoit
  • Patent number: 8878331
    Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael Gros-Jean, Clement Gaumer, Emmanuel Bayard Perrin
  • Patent number: 8802575
    Abstract: A method for forming the gate insulator of a MOS transistor, including the steps of: a) forming a thin silicon oxide layer at the surface of a semiconductor substrate; b) incorporating nitrogen atoms into the silicon oxide layer by plasma nitridation at a temperature lower than 200° C., to transform this layer into a silicon oxynitride layer; and c) coating the silicon oxynitride layer with a layer of a material of high dielectric constant, wherein steps b) and c) follow each other with no intermediate anneal step.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: August 12, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Gourhant, David Barge, Clément Gaumer, Mickaël Gros-Jean
  • Publication number: 20120270410
    Abstract: A method for forming the gate insulator of a MOS transistor, including the steps of: a) forming a thin silicon oxide layer at the surface of a semiconductor substrate; b) incorporating nitrogen atoms into the silicon oxide layer by plasma nitridation at a temperature lower than 200° C., to transform this layer into a silicon oxynitride layer; and c) coating the silicon oxynitride layer with a layer of a material of high dielectric constant, wherein steps b) and c) follow each other with no intermediate anneal step.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 25, 2012
    Inventors: Olivier Gourhant, David Barge, Clément Gaumer, Mickaël Gros-Jean