Patents by Inventor Clément Merckling
Clément Merckling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9425314Abstract: A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h?, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.Type: GrantFiled: March 5, 2014Date of Patent: August 23, 2016Assignee: IMECInventors: Clement Merckling, Matty Caymax
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Publication number: 20160240532Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: ApplicationFiled: April 25, 2016Publication date: August 18, 2016Inventors: Niamh Waldron, Clement Merckling, Nadine Collaert
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Patent number: 9419110Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.Type: GrantFiled: November 11, 2015Date of Patent: August 16, 2016Assignee: IMEC VZWInventors: Clement Merckling, Nadine Collaert
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Publication number: 20160141391Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.Type: ApplicationFiled: November 11, 2015Publication date: May 19, 2016Applicant: IMEC VZWInventors: Clement Merckling, Nadine Collaert
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Patent number: 9324818Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: GrantFiled: March 27, 2015Date of Patent: April 26, 2016Assignee: IMEC VZWInventors: Niamh Waldron, Clement Merckling, Nadine Collaert
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Publication number: 20150333122Abstract: An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.Type: ApplicationFiled: May 18, 2015Publication date: November 19, 2015Applicant: IMEC VZWInventors: Boon Teik Chan, Clement Merckling
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Publication number: 20150279947Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: ApplicationFiled: March 27, 2015Publication date: October 1, 2015Inventors: Niamh Waldron, Clement Merckling, Nadine Collaert
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Patent number: 9082616Abstract: The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.Type: GrantFiled: May 15, 2014Date of Patent: July 14, 2015Assignee: IMECInventor: Clement Merckling
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Patent number: 8994109Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial ?-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.Type: GrantFiled: March 15, 2013Date of Patent: March 31, 2015Assignees: STMicroelectronics SA, Centre National de la Recherche Scientifique, Ecole Centrale de LyonInventors: Clement Merckling, Mario El-Kazzi, Guillaume Saint-Girons, Guy Hollinger
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Publication number: 20140339680Abstract: The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.Type: ApplicationFiled: May 15, 2014Publication date: November 20, 2014Applicant: IMECInventor: Clement Merckling
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Patent number: 8872238Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.Type: GrantFiled: October 17, 2012Date of Patent: October 28, 2014Assignee: IMECInventor: Clement Merckling
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Publication number: 20140252414Abstract: A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h?, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.Type: ApplicationFiled: March 5, 2014Publication date: September 11, 2014Applicant: IMECInventors: Clement Merckling, Matty Caymax
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Publication number: 20130200440Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial ?-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.Type: ApplicationFiled: March 15, 2013Publication date: August 8, 2013Applicants: STMICROELECTRONICS S.A., ECOLE CENTRALE DE LYON, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE -CNRSInventors: Clement Merckling, Mario El-Kazzi, Guillaume Saint-Girons, Guy Hollinger
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Patent number: 8426261Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial ?-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.Type: GrantFiled: August 28, 2007Date of Patent: April 23, 2013Assignees: STMicroelectronics S.A., Centre National de la Recherche Scientifique, Ecole Centrale de LyonInventors: Clément Merckling, Mario El-Kazzi, Guillaume Saint-Girons, Guy Hollinger
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Publication number: 20130043508Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.Type: ApplicationFiled: October 17, 2012Publication date: February 21, 2013Inventor: Clement Merckling
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Patent number: 8314017Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.Type: GrantFiled: October 1, 2010Date of Patent: November 20, 2012Assignee: IMECInventor: Clement Merckling
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Patent number: 8232581Abstract: Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.Type: GrantFiled: June 24, 2010Date of Patent: July 31, 2012Assignee: IMECInventors: Geoffrey Pourtois, Clement Merckling, Guy Brammertz, Matty Caymax
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Publication number: 20110089469Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.Type: ApplicationFiled: October 1, 2010Publication date: April 21, 2011Applicant: IMECInventor: Clement Merckling
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Publication number: 20100327316Abstract: Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.Type: ApplicationFiled: June 24, 2010Publication date: December 30, 2010Applicant: IMECInventors: Geoffrey Pourtois, Clement Merckling, Guy Brammertz, Matty Caymax
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Publication number: 20100301420Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial ?-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.Type: ApplicationFiled: August 28, 2007Publication date: December 2, 2010Inventors: Clément Merckling, Mario El-Kazzi, Guillaume Saint-Girons, Guy Hollinger