Patents by Inventor Claire Gallon

Claire Gallon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7915110
    Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: March 29, 2011
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat à l'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Benouillet-Beranger
  • Publication number: 20100230755
    Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced. An upper surface of the substrate and an upper surface of the isolating region are flush with each other so as to define a planar surface on which the transistor gate region is formed.
    Type: Application
    Filed: May 25, 2010
    Publication date: September 16, 2010
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat a L'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
  • Patent number: 7749858
    Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: July 6, 2010
    Assignees: STMicroelectronics (Crolles 2) SAS, Commisssariat a l'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
  • Patent number: 7635615
    Abstract: Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the side parts, a grid, separated from the channel by a grid insulator.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: December 22, 2009
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Jean-Charles Barbe, Sylvian Barraud, Claire Fenouillet-Beranger, Claire Gallon, Aomar Halimaoui
  • Publication number: 20090224295
    Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.
    Type: Application
    Filed: March 27, 2009
    Publication date: September 10, 2009
    Applicants: STMicroelectronics (Crolles) 2 SAS, Commissariat A L'energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
  • Patent number: 7556995
    Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: July 7, 2009
    Assignees: STMicroelectronics Crolles 2 SAS, Commissariat a l'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
  • Publication number: 20070122975
    Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 31, 2007
    Applicants: STMicroelectronics Crolles 2 SAS, Commissariat a l'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillei-Beranger
  • Publication number: 20070037324
    Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced.
    Type: Application
    Filed: July 17, 2006
    Publication date: February 15, 2007
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat a L'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
  • Publication number: 20070001227
    Abstract: Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the side parts, a grid, separated from the channel by a grid insulator.
    Type: Application
    Filed: June 16, 2006
    Publication date: January 4, 2007
    Inventors: Jean-Charles Barbe, Sylvian Barraud, Claire Fenouillet-Beranger, Claire Gallon, Aomar Halimaoui