Patents by Inventor Claire Ravit

Claire Ravit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100230673
    Abstract: The invention relates to a semiconductor fuse structure comprising a substrate (1) having a surface, the substrate (1) having a field oxide region (3) at the surface, the fuse structure further comprising a fuse body (FB), the fuse body (FB) comprising polysilicon (PLY), the fuse body (FB) lying over the field oxide region (3) and extending into a current-flow direction (CF), wherein the fuse structure is programmable by means of leading a current through the fuse body (FB), wherein the fuse body (FB) has a tensile strain in the current-flow direction (CF) and a compressive strain in a direction (Z) perpendicular to said surface of the substrate (1). The invention further relates to methods of manufacturing such a semiconductor fuse.
    Type: Application
    Filed: June 6, 2007
    Publication date: September 16, 2010
    Applicant: NXP B.V.
    Inventors: Claire Ravit, Tobias S. Doorn
  • Patent number: 7554138
    Abstract: The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of silicon and germanium and a thickness such that the lattice is substantially relaxed, and on top of the first semiconductor layer (1) a second semiconductor layer (2) is provided comprising strained silicon, in which layer (2) a part of the semiconductor device (10) is formed, and wherein measures are taken to avoid reduction of the effective thickness of the strained silicon layer (2) during subsequent processing needed to form the semiconductor device (10), said measures comprising the use of a third layer (3) having a lattice of a mixed crystal of silicon and germanium.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: June 30, 2009
    Assignee: NXP B.V.
    Inventors: Philippe Meunier-Beillard, Claire Ravit
  • Publication number: 20070246742
    Abstract: The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of silicon and germanium and a thickness such that the lattice is substantially relaxed, and on top of the first semiconductor layer (1) a second semiconductor layer (2) is provided comprising strained silicon, in which layer (2) a part of the semiconductor device (10) is formed, and wherein measures are taken to avoid reduction of the effective thickness of the strained silicon layer (2) during subsequent processing needed to form the semiconductor device (10), said measures comprising the use of a third layer (3) having a lattice of a mixed crystal of silicon and germanium.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 25, 2007
    Applicant: KONINKLIJIKE PHILIPS ELECTRONICS N.V.
    Inventors: Philippe Meunier-Beillard, Claire Ravit
  • Patent number: 7157349
    Abstract: A method of manufacturing a semiconductor device comprising a silicon body (1) having a surface (4) provided with field isolation regions (2) enclosing active regions (3). In this method, on the surface of the silicon body there is formed an auxiliary layer (5) of a material on which, during an oxidation treatment, a thicker layer of silicon oxide is formed than on the silicon of the silicon body. Here, an auxiliary layer comprising silicon and germanium is formed on the surface, said auxiliary layer preferably being a layer of SixGe1?x?yCy, where 0.70<x<0.95 and y<0.05. Next, at the location of the field isolation regions to be formed, windows (9) are formed in the auxiliary layer and trenches (11) are formed in the silicon body. Next, on the walls (12) of the trenches, a silicon oxide layer (13) is provided and on the walls (10) of the windows a silicon oxide layer (14) is provided, both being formed by an oxidation treatment. The auxiliary layer is not oxidized throughout its thickness.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: January 2, 2007
    Assignee: NXP B.V.
    Inventors: Jurriaan Schmitz, Claire Ravit, Rita Victoire Theodosie Rooyackers