Abstract: A SONET framer with multiple clock-crossing capability for use in an optical cross-connect system. The input stage of the cross-connect includes a framer ASIC that performs both frame alignment of multiple data streams and retimes them with a system clock at a same frequency. The ASIC processes multiple clocks from PLL's and retimes the data with the system clock at the same frequency. The present invention nests the clock crossing function in the frame alignment function in order to align all the incoming data streams with the system clock. Advantages include reduced chip area and reduced power consumption.

Abstract: The present invention achieves technical advantages as a FEC decoder. The FEC decoder is made up of a top level controller and individual FEC bit decoders. The top level controller has a state machine for the decoder, and sends out enable signals to the individual bit decoders. In the preferred embodiment, the total delay through the decoding system is only about 14.6 microseconds. Each bit decoder preferably includes a main controller, 3 syndrome generator blocks, a controller for syndrome checkers, 3 syndrome checking blocks, a block to calculate sigma 2, a block to calculate sigma 3, a Chien search block, a storage block, an error correction block, an error counting block, a data selection block, and a decoder status block. The blocks meet all the requirements of Standard T1×1.5/99-R218R3 and operates with both OC-48 and OC-192 data.

Abstract: The present invention achieves technical advantages as an in-band FEC encoder circuit that is comprised of individual bit FEC encoders. The total delay through the encoding circuit is nominal. The encoder circuit consists of a controller block, a checkbit generator block, a controller state machine block, an FSI bit insertion block, two different blocks to insert in checkbits, and a selection block. These blocks meet all the requirements of the Standard T1X1.5/99-218R3 and operates with both OC-48 and OC-192. In one embodiment, the total delay through the encoding system is only 14 microseconds.

Abstract: The present invention achieves technical advantages as an in-band FEC syndrome generator and computation circuit. Three syndrome generators are utilized to generate 3 syndromes comprising polynomials. Each syndrome generator is comprised of two linear feedback shift registers (LFSR). Each LFSR operates in both 4-bit parallel mode and a 1-bit serial 39 bit mode. The two LFSRs work together to allow data to continuously be shifted in and the syndrome be generated. The first LFSR shifts in information bits, and at the end of each message, after the information bits have been shifted in, the first LFSR dumps its contents into the second LFSR. This second LFSR shifts in the 39 checkbits which performs the modulus operation. The contents of the second LFSR contain the syndrome once the checkbits have been shifted in. Then, these checkbits are shifted out, 4 bits at a time.