Abstract: A power reduction system for a UART system having a controllable oscillator for producing free-running clock signals. A controlled clock synchronizer having an output terminal is coupled to the oscillator and responsive to both a first control signal thereto and application of the free-running clock signals thereto to provide synchronized pulses and is responsive to both a second control signal different from the first control signal thereto and application of the free-running clock signals thereto to cease production of the synchronized pulses at the output terminal. A UART core controls the oscillator and the clock synchronizer and is operated under control of clock signals from the clock synchronizer. The controllable oscillator includes an inverter having a feedback circuit thereacross including a switch responsive to the third control signal to cause the oscillator to cease oscillation.

Abstract: A method and apparatus for a circuit physically realizing a Universal Asynchronous Receive/Transmit (UART) circuit 31, 40 having an automatic flow control feature. A preferred embodiment includes a UART 31 provided with additional control circuitry 39, 34 for automatically pausing transfers from the transmit data circuitry 35, 32 in response to a transition at the CTS (Clear to Send) input, and further provided with control circuitry 39 for automatically asserting and deasserting a RTS (Ready to Send) output when a receiver data threshold is reached.

Abstract: A glitch filter identifies and eliminates positive edge and negative edge glitches without utilizing a high frequency sampling clock. The glitch filter comprises a programmable delay buffer string, two multiple input AND gates and a latch. The buffer string provides a plurality of incrementally delayed signals and utilizes them as signal samples thus simulating a high frequency sampling clock. The two multiple input AND gates serve to eliminate positive or negative edge glitches. The latch outputs the accurate filtered data without any positive or negative edge glitches.