Patents by Inventor Clarence K. L. Tam

Clarence K. L. Tam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8948325
    Abstract: A method and apparatus to digitally remove in-band non-linear signal distortion caused by a radio frequency (RF)/intermediate frequency (IF) receiver circuit that has non-linearities, which are further affected by low-IF ADC sample aliasing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventors: William D. Warner, Clarence K. L. Tam
  • Patent number: 8327204
    Abstract: A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently phased clock signals to generate a phase-modulated signal. The phase-selecting signal is designed to contain low- and high-frequency components. The phase-modulated signal is input into a phase filter to filter unwanted high-frequency components. The filtered output of the phase filter is input into a data-transmit serializer to serialize a low-speed parallel word into a high-speed jittered test pattern for input into the transceiver circuitry.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: December 4, 2012
    Assignee: DFT Microsystems, Inc.
    Inventors: Mohamed M. Hafed, Sebastien Laberge, Bardia Pishdad, Clarence K. L. Tam
  • Patent number: 7242209
    Abstract: A module (236, 236?) containing an integrated testing system (108) that includes one or more measurement engines (200, 202) tightly coupled with a compute engine (208). The one or more measurement engines include at least one stimulus instrument (212) for exciting circuitry of a device-under-test (104) with one or more stimulus signals, and at least one measurement instrument (216) that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry (800) for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine (204) providing two-way communications between the integrated testing system automated testing equipment (116) and/or a dedicated user interface (140) residing on a host computer (136).
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: July 10, 2007
    Assignee: DFT Microsystems, Inc.
    Inventors: Gordon W. Roberts, Antonio H. Chan, Geoffrey D. Duerden, Mohamed M. Hafed, Sébastien Laberge, Bardia Pishdad, Clarence K. L. Tam
  • Patent number: 6917320
    Abstract: A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: July 12, 2005
    Assignee: McGill University
    Inventors: Gordon W. Roberts, Clarence K. L. Tam
  • Publication number: 20040246002
    Abstract: A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal, at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point.
    Type: Application
    Filed: April 26, 2004
    Publication date: December 9, 2004
    Applicant: McGill University
    Inventors: Gordon W. Roberts, Clarence K.L. Tam
  • Patent number: 6727834
    Abstract: A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: April 27, 2004
    Assignee: McGill University
    Inventors: Gordon W. Roberts, Clarence K. L. Tam
  • Publication number: 20030206127
    Abstract: A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point.
    Type: Application
    Filed: May 1, 2003
    Publication date: November 6, 2003
    Inventors: Gordon W. Roberts, Clarence K.L. Tam