Abstract: A method for protecting a dynamically reconfigurable computing system includes generating an encoding signature and passing the encoding signature, through a system level bus, to at least one field programmable logic device and to a function library included within the system. The function library contains a plurality of functions for selective programming into the at least one field programmable logic device. A lock is generated so as to prevent external resources with respect to the system from accessing the encoding signature during the passing thereof.

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB 1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract: A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

Abstract: A new hardware description language (HDL) extension at the register-transfer level (RTL) for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for the fault tolerant logic functions. Code (20) is written in VHDL at the RTL and includes instructions for adding the operator “FT” to certain logic functions. Logic functions that include the FT operator are considered critical functions, i.e., fault tolerant. By including the FT operator, a logic synthesis tool is alerted to the functions that have been designated as fault tolerant. As a result, the preprogrammed logic synthesis tool causes the design of the IC to include a fault redundant scheme (30) for the logic functions that include the FT operator. Fault redundant scheme (30) includes three copies of the logic function, i.e., Copy A (32), Copy B (34), and Copy C (36), as well as a majority voter 38.

Abstract: A method and system for modifying the function of a state machine having a programmable logic device. The method including: (a) modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; (b) generating a programmable logic device netlist from differences in the high-level design and the modified design; and (c) installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract: In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.

Abstract: In a first aspect of the invention, a first method is provided for aligning signals from a first receiver located in a first clock domain to a second receiver located in a second clock domain. The first method includes the steps of creating a programmable delay element between the first and second receivers, and selectively adding delay via the programmable delay element to the signals until the signals are aligned. Numerous other aspects are provided.

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line.