Abstract: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: A bus bridge for coupling between a first bus and a second bus includes: a number of data buffers for a particular request type; a counter for monitoring a number of requests of the particular type received at the bus bridge from the first bus for access to the second bus; and override logic. Each request of the particular type requires one data buffer of the number of data buffers for the particular request type. The override logic determines when the monitored number of requests of the particular type exceeds the number of data buffers for the particular request type at the bus bridge, and responsive thereto, initiates a request termination signal at the bus bridge to terminate a received request of the particular type. When request coherency is maintained employing snooping, the request termination signal is a retry snoop response signal output from the bus bridge.

Abstract: In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.

Abstract: A bus bridge for coupling between a first bus and a second includes: at least one data buffer; data load logic and data unload logic. The data load logic places received data in the at least one data buffer, wherein the data is received at the bus bridge from across the first bus in a first data ordering. The data unload logic automatically translates the received data from the first data ordering to a second data ordering during unloading of the data from the at least one data buffer for transfer across the second bus, wherein the first data ordering and the second data ordering are each a different one of a linear data ordering and an interleaved data ordering.

Abstract: A bus bridge for coupling between a first bus and a second bus includes: multiple ticket registers; a ticket dispenser counter; and a ticket call counter. The ticket dispenser counter dispenses a ticket value to a request received at the bridge from the first bus for access to the second bus. This ticket value is held in one ticket register of the multiple ticket registers. The ticket call counter provides ticket call values, and the request is granted access to the second bus when a current ticket call value equals the ticket value dispensed to the request. While the request waits for access to the second bus, the bus bridge can perform work on the request. When request coherency is maintained employing snooping, ticket values assigned to a plurality of requests maintain a snoop response ordering of the requests for access to the second bus.

Abstract: A new hardware description language (HDL) extension at the register-transfer level (RTL) for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for the fault tolerant logic functions. Code (20) is written in VHDL at the RTL and includes instructions for adding the operator “FT” to certain logic functions. Logic functions that include the FT operator are considered critical functions, i.e., fault tolerant. By including the FT operator, a logic synthesis tool is alerted to the functions that have been designated as fault tolerant. As a result, the preprogrammed logic synthesis tool causes the design of the IC to include a fault redundant scheme (30) for the logic functions that include the FT operator. Fault redundant scheme (30) includes three copies of the logic function, i.e., Copy A (32), Copy B (34), and Copy C (36), as well as a majority voter 38.

Abstract: A method and system for modifying the function of a state machine having a programmable logic device. The method includes the steps of modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; generating a programmable logic device netlist from differences in the high-level design and the high-level modified design; and installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line.

Abstract: A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract: Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.

Abstract: A method, system and media for communicating with and controlling design logic modules (“cores”) which are external to a system-on-chip (“SOC”) design during verification of the design. An external memory-mapped test device (“EMMTD”) is coupled between a SOC design being tested in simulation, and cores external to the SOC design. Internal logic in the EMMTD provides for control and status monitoring of an external core coupled to an EMMTD bi-directional bus by enabling functions including driving data on the bus, reading the current state of data on the bus, and capturing positive and negative edge transitions on the bus.

Abstract: A memory card having a memory bus controller is provided which card has a signal processing element preferably a digital signal processor (DSP) thereon, which card is used in a computer system as add-on memory. Also, a method of using such a card in a computer system is provided. The memory bus controller and the signal processing element are programmed to pass all the addresses in the memory on the card and the associated data received from the CPU to the signal processing element where they are stored in memory. The signal processing element is programmed to perform selected operations on the addresses and/data irrespective of whether the signal processing element has control of the system bus. These operations can include keeping track of read/write operations and the locations of these operations. This information can be easily accessed by the computer system and used for memory optimization. The DSP can also “snoop” the memory bus when it is unavailable to the control of the DSP, i.e.

Abstract: A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data.

Abstract: A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data.

Abstract: A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data.

Abstract: A system and method for arbitrating amongst a plurality of applications requesting bus access. Based on the applications requesting bus access, a bus frame is calculated, and a plurality of bus duration time slots within the bus frame are determined. For each bus duration time slot, a priority is assigned to each application requesting bus control and a bus allocation table is created. A bus master controller then allocates control during each bus duration time slot in accordance with the priorities in the bus allocation table.

Abstract: According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

Abstract: A system for managing the flow of real time data streams into a data system cache memory is disclosed. The data system includes a central processing unit or micro controller, with a cache memory, which operates at a relatively fast operating speed, near that of the central processing unit. An interrupt controller is provided as well as a quantization timer that disables the interrupts to the CPU during an execution quantization (EQ) period, and allows the interrupts to pass at an EQ boundary. In operation, the quantization timer controls interrupts to occur only when cache load actions are at a specific quantized time, thus ensuring that a given task in the cache will execute or load for a given quantized length of time, and therefore, the possibility of loading a cache randomly only to execute a few instructions is eliminated.

Abstract: A plurality of multipliers for multiplying numbers having B number of bits are provided for multiplying A-operands having B number of bits by a B-operand having B number of bits. Pairs of A- and B-operands are loaded into each multiplier. Each of the multipliers calculates an intermediate result by internally adding B number of partial products. In response to the data processing system being operated in a signed mode, selected bits in selected partial products in selected multipliers are complemented, and 2.sup.B is added to a selected intermediate result so that when the intermediate results are appropriately weighted and added together, a result that is the product of two operands having 2B-bits may be calculated. In another mode, multiple products having B-bits are calculated from the pairs of A- and B-operands. The A- and B-operands may be either signed or unsigned.