Abstract: A method is provided for making a solar cell. The method includes providing a stack including a substrate, a barrier layer disposed on the substrate, and an anti-reflective layer disposed on the barrier layer, where the anti-reflective layer has charge centers. The method also includes generating a corona with a charging tool and contacting the anti-reflective layer with the corona thereby injecting charge into at least some of the charge centers in the anti-reflective layer. Ultra-violet illumination and temperature-based annealing may be used to modify the charge of the anti-reflective layer.

Abstract: A method is provided for making a solar cell. The method includes providing a stack including a substrate, a barrier layer disposed on the substrate, and an anti-reflective layer disposed on the barrier layer, where the anti-reflective layer has charge centers. The method also includes generating a corona with a charging tool and contacting the anti-reflective layer with the corona thereby injecting charge into at least some of the charge centers in the anti-reflective layer. Ultra-violet illumination and temperature-based annealing may be used to modify the charge of the anti-reflective layer.

Abstract: A method of reducing an inter-atomic bond strength in a substance includes the steps of: providing a target material (110, 910, 1210, 1260, 1410, 1460); exposing the target material to a particle flood (140); and annealing the target material while exposing the target material to the particle flood. As an example, the target material can be a collection of non-activated dopant atoms within a semiconducting material. As another example, the target material can be a semiconducting material in an amorphous form. In a different embodiment of the invention an electrically conducting material (950, 1250, 1270, 1450, 1470, 1480) is used as an electron source rather than a particle flood, and an electrically conducting diffusion barrier (940) is placed between the electrically conducting material and the target material.

Abstract: A method for damage avoidance in transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled to happen within the buried strained layer in conjunction with the introduction of hydrogen.

Abstract: A method of forming III-V epitaxy on a germanium-on-insulator (GOI) substrate having a bonded layer and a handle substrate begins with measuring a lattice parameter of the bonded layer at a first temperature. The lattice parameter of the bonded layer, which is a function of a coefficient of thermal expansion (CTE) of the handle substrate, is then calculated at an epitaxial growth temperature. An epitaxial composition is selected from a class of III-V material for epitaxial growth overlying the bonded layer, wherein the selected epitaxial composition is adjusted to have a lattice parameter that approximates the calculated lattice parameter of the bonded layer at the epitaxial growth temperature. An epitaxial layer can then be grown over the bonded layer with use of the adjusted epitaxial composition, producing a substantially defect-free III-V epitaxial layer. Furthermore, an improved defectivity is claimed when the epitaxial layer's CTE is approximately similar to that of the handle substrate.

Abstract: Methods for fabricating high work function p-MOS device metal electrodes are provided. In one embodiment, a method is provided for producing a metal electrode including the steps of: providing a high k dielectric stack with an exposed surface; contacting the exposed surface of the high k dielectric stack with a vapor of a metal oxide wherein the metal oxide is selected from the group consisting of RuOx, IrOx, ReOx, MoOx, WOx, VOx, and PdOx; and contacting the exposed surface of the dielectric stack with a vapor of an additive selected from the group consisting of SiO2, Al2O3, HfO2, ZrO2, MgO, SrO, BaO, Y2O3, La2O3, and TiO2, whereby contacting the exposed surface of the dielectric stack with the vapor of the metal oxide and the vapor of the additive forms an electrode and wherein the additive is present at an amount between about 1% to about 50% by atomic weight percent in the electrode.

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Abstract: A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure is provided. The method includes forming a mask layer overlying the electrically conductive electrode and patterning the mask layer to form an exposed electrically conductive electrode material. At least a portion of the exposed electrically conductive electrode material is removed while an electrically conductive veil is formed adjacent the mask layer. A metal contact layer is formed such that said metal contact layer contacts the electrically conductive veil.

Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.