Abstract: In a plural processor data processing system, a lock is obtained on a commonly shared storage means that allows for the testing of a control word associated with a selected memory address of a particular data processor wherein each of the data processors of the system is capable of independently requesting a lock on said control word. Lock requests are broadcast to each of the data processors. The lock is then established according to predefined criteria by transmission of the lock requests of all of said processor means at the same time at controlled intervals, and by providing the lock on the control word when the requesting processor is the only processor that is requesting a given control word during a control interval, or when the processor transmits its lock request simultaneously with other processor means of a lower priority.

Abstract: A high-speed partitioned set associative cache memory is provided with a plurality of cache memory boards. Each of the boards is provided with a partial data array and a full tag array on each board. At least one memory address register is mounted on each of the boards with the partial data array and the full tag array for receiving a unique address from the central processing unit which enables the plurality of memory address registers to simultaneously access addresses in the partial data arrays on different boards and to also address tag addresses associated with the data addresses by sequencing controls mounted on a separate board with logic circuits which monitor output signals from the data arrays and the tag arrays. The output signals resulting from accessing memory locations in the cache memory are coupled to logic circuits for determining the type of error and the exact array where a single error has occurred.

Abstract: A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.

Abstract: A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting system provides field selection and justification together with the capability of complementing and magnitude generation of the selected fields. Floating-point operands in two different floating-point formats can be unpacked, that is the characteristic separated from the mantissa and properly aligned, and can be packed by positioning and recombining the characteristic with that associated mantissa. Throughout the entire reformatting process, parity for selected bit groupings is maintained, thereby allowing through checking of reformatting operations. The reformatting system includes programmably selectable constant generation.

Abstract: A data processing system is provided with multiple system clock sources operating at different frequencies for selectively and synchronously driving a plurality of clock pulse generators. The clock pulse generators include four-stage ring counters which may be controlled to produce either four or eight phase clocking signals. When a change is to be made from one system clock source to another, the clock pulse generators are stopped. A phase capture register stores an indication of the last phase generated. While the clock pulse generators are stopped, the change over to the new system clock source is made. The clock pulse generators are restarted at a first time or a second, later time depending upon whether the stored phase indication indicates that the clock pulse generators were stopped at one of phases 5-8 or one of phases 1-4.

Abstract: A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is additionally provided to regenerate original source parity from the matrix outputs for use in thru checking. A single 9-bit parity generator is all that is required to check the correctness of the matrix.