Abstract: A unique memory output integrated circuit disclosed including a memory output driver having an output terminal at which data may be read, a gated power amplifier, and a single ended multiplexer stage which, in the preferred embodiment, is adapted to be interfaced with a random access memory array comprised of a plurality of discrete, non-symmetrical memory cells. The integrated circuit is designed so that the space consumed thereby and the corresponding cost of production can be minimized.

Abstract: An improved very high speed, static random access memory cell disclosed which is comprised of complementary metal oxide semiconductor field effect transistors which may be formed by silicon on sapphire techniques. To maximize the speed of the read operation while, at the same time, decreasing the overall cell area and consequently the cost, the cell is made highly non-symmetrical in design. As an example, selected ones of the semiconductor transistors may have reduced channel widths with respect to one another.

Abstract: Unique, relatively simplified circuits employing complementary metal oxide semiconductor transistors and suitable diode means to mechanize the Boolean functions A.sup.. B and A+B and combinations thereof. In a preferred embodiment, the transistors and diodes may be fabricated by silicon-on-sapphire integrated circuit techniques. The circuits obviate the need for a conventional NOR or NAND gate which is common to logic gating arrangements of the prior art. Hence, the number of components and the corresponding cost of the circuit are reduced while the operating speed thereof is increased.

Abstract: A uniquely arranged, clock-controlled integrated circuit is disclosed as a building block for implementing Boolean logic functions. The circuit has a minimum number of components and a design to yield a low cost, high speed operation. The circuit may also include an efficient signal inversion and amplification stage, where such is required.

Abstract: A solid state memory employs a plurality of memory cells each capable of storing either of two different binary values. The memory cells require periodic application of a refresh pulse to the memory cell to, without rewriting, enhance at least one of the two different binary values which the memory cells can store, in order to prevent loss of that binary value over a period of time. The reliability of the memory is improved by supplying a refresh signal which includes a plurality of refresh pulses in each memory cycle.