Abstract: Systems and methods of verifying a hardware processing circuit design for a digital system are disclosed. Three different computer models of the same hardware are implemented. The first computer model is implemented on a first sequence of action inputs and a second sequence of action inputs. The second computer model is implemented on the first sequence of action inputs and is allowed to idle until the first sequence is done. The architectural states of the second computer model are then recorded. The third computer model is implemented on the second sequence after having set the third computer model to the recorded architectural states. The outputs of the first computer model and the third computer model are implemented to check for functional consistency. The techniques described herein can be used to check digital designs for functional consistency, are sound and complete, and do not require an understanding of implementation details.

Abstract: Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called “change detectors” which introduce only a small area overhead.

Abstract: Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called “change detectors” which introduce only a small area overhead.

Abstract: A computer is programmed in accordance with the invention to automatically analyze a digital circuit, to check if the digital circuit can enter a target state starting from a start state, by reusing information learned during a another analysis, checking if the same digital circuit can enter the same or different target state from a different start state. Use of learned information in accordance with the invention simplifies the analysis of the digital circuit (e.g. by allowing skipping one or more analysis acts). The learned information may be stored in a database. Depending on the embodiment, the two or more analyses may check on operation of the digital circuit for the same or different numbers of cycles.