Patents by Inventor Clark H. Jarvis

Clark H. Jarvis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8621322
    Abstract: Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)?K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)?K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 31, 2013
    Assignee: FreeScale Semiconductor, Inc.
    Inventors: Mohit K. Prasad, Clark H. Jarvis
  • Publication number: 20100083072
    Abstract: Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)?K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)?K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Mohit K. Prasad, Clark H. Jarvis
  • Patent number: 7539272
    Abstract: Different from conventional equalizers, the output of an SAIC (Single Antenna Interference Cancellation) linear equalizer in GSM/EDGE wireless communication systems is a real signal combined from two real FIR (Finite Impulse Response) filter outputs. Each of the FIRs separately uses the real and imaginary components of the ½ ? de-rotated received signal as input. The real-valued output of the SAIC equalizer creates difficulty to estimate and correct the frequency errors due to receiver LO and Doppler shift. Disclosed is an efficient and effective solution to the estimation and correction of the frequency error through an assistant signal generated by two additional FIR filters. The assistant signal and the SAIC equalizer output are used to estimate the frequency error, which is combined with the SAIC equalizer output and the assistant signal to give the frequency error corrected SAIC equalizer output.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: May 26, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weizhong Chen, Clark H. Jarvis