Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

Abstract: A prednisone enteric-coated preparation and a preparation method and use thereof are provided. The prednisone enteric-coated preparation includes: 5% to 35% of an active prednisone micro-enteric-coated preparation unit, such as an enteric-coated microsphere; and an inactive pharmaceutical adjuvant. The enteric-coated microsphere has an average particle size of 100 ?m to 1,000 ?m, and a dissolution behavior of the enteric-coated microsphere conforms to the provisions for enteric-coated preparations. The enteric-coated microsphere characteristic not only avoids the stimulation of prednisone to a gastric mucosa, but also makes the active ingredient quickly released and absorbed in an intestinal tract to prevent the active ingredient from being destroyed by intestinal floras. The prednisone enteric-coated preparation can be any dosage form such as a suspension or a capsule suitable for patients with difficult swallowing or normal patients.

Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

Abstract: An optical test method is provided. The optical test method includes emitting light through a gap between two substrates of a tested optical element disposed on a holder to generate a plurality of light beams. The optical test method further includes driving the holder with the tested optical element to move to N positions. The optical test method also includes receiving one of the light beams from the tested optical element in the N positions to generate N first intensity signals. In addition, the optical test method includes determining the size of the gap of the tested optical element according to the N first intensity signals and reference data.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.