Patents by Inventor Clark Nelson

Clark Nelson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220275275
    Abstract: According to some embodiments, an apparatus and method are provided comprising: an enclosure defining a cavity within the enclosure, the cavity comprising a depth dimension; at least one LED chip; a layer comprising a blend of an encapsulant material and phosphor composition, the layer overlaying the at least one LED chip and disposed within the cavity; the phosphor composition comprising a yellow-green phosphor and a Mn4+ doped complex fluoride phosphor of formula I, Ax[MFy]:Mn4+ (I) where A is Li, Na, K, Rb, Cs, NR4 or a combination thereof; M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; R is H, lower alkyl, or a combination thereof; x is the absolute value of the charge of the [Mfy] ion; and y is 5, 6, or 7; wherein the Mn4+ doped complex fluoride phosphor of formula I comprises a d50 particle size of from about 1 micrometers to about 10 micrometers, and the LED lighting apparatus, when activated, emits visible light comprising a correlated color temperature (
    Type: Application
    Filed: July 30, 2020
    Publication date: September 1, 2022
    Inventors: Jenna Marie Baldesare, Fangming Du, Ashfaqul Islam Chowdhury, Rick Dean Dureiko, Clark Nelson
  • Patent number: 10642587
    Abstract: Technologies for indirectly calling vector functions include a compute device that includes a memory device to store source code and a compiler module. The compiler module is to identify a set of declarations of vector variants for scalar functions in the source code, generate a vector variant address map for each set of vector variants, generate an offset map for each scalar function, and identify, in the source code, an indirect call to the scalar functions, wherein the indirect call is to be vectorized. The compiler module is also to determine, based on a context of the indirect call, a vector variant to be called and store, in object code and in association with the indirect call, an offset into one of the vector variant address maps based on (i) the determined vector variant to be called and (ii) the offset map that corresponds to each scalar function.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Hideki Saito Ido, Serge V. Preis, Sergey S. Kozhukhov, Xinmin Tian, Sergey V. Maslov, Clark Nelson, Jianfei Yu
  • Publication number: 20190050212
    Abstract: Technologies for indirectly calling vector functions include a compute device that includes a memory device to store source code and a compiler module. The compiler module is to identify a set of declarations of vector variants for scalar functions in the source code, generate a vector variant address map for each set of vector variants, generate an offset map for each scalar function, and identify, in the source code, an indirect call to the scalar functions, wherein the indirect call is to be vectorized. The compiler module is also to determine, based on a context of the indirect call, a vector variant to be called and store, in object code and in association with the indirect call, an offset into one of the vector variant address maps based on (i) the determined vector variant to be called and (ii) the offset map that corresponds to each scalar function.
    Type: Application
    Filed: March 11, 2016
    Publication date: February 14, 2019
    Inventors: Hideki Saito IDO, Serge V. PREIS, Sergey S. KOZHUKHOV, Xinmin TIAN, Sergey V. MASLOV, Clark NELSON, Jianfei YU
  • Patent number: 8719839
    Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit) GPU, for example. The GPU may be coupled to a GPU compiler and a GPU linker/loader and the CPU may be coupled to a CPU compiler and a CPU linker/loader. The user may create a shared object in an object oriented language and the shared object may include virtual functions. The shared object may be fine grain partitioned between the heterogeneous processors. The GPU compiler may allocate the shared object to the CPU and may create a first and a second enabling path to allow the GPU to invoke virtual functions of the shared object. Thus, the shared object that may include virtual functions may be shared seamlessly between the CPU and the GPU.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: May 6, 2014
    Assignee: Intel Corporation
    Inventors: Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Mohan Rajagopalan, Rajiv Deodhar, David Putzolu, Clark Nelson, Milind Girkar, Robert Geva, Tiger Chen, Sai Luo, Stephen Junkins, Bratin Saha, Ravi Narayanaswamy, Patrick Xi
  • Publication number: 20130061240
    Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit) GPU, for example. The GPU may be coupled to a GPU compiler and a GPU linker/loader and the CPU may be coupled to a CPU compiler and a CPU linker/loader. The user may create a shared object in an object oriented language and the shared object may include virtual functions. The shared object may be fine grain partitioned between the heterogeneous processors. The GPU compiler may allocate the shared object to the CPU and may create a first and a second enabling path to allow the GPU to invoke virtual functions of the shared object. Thus, the shared object that may include virtual functions may be shared seamlessly between the CPU and the GPU.
    Type: Application
    Filed: October 30, 2009
    Publication date: March 7, 2013
    Inventors: Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Mohan Rajagopalan, Rajiv Deodhar, David Putzolu, Clark Nelson, Milind Girkar, Robert Geva, Tiger Chen, Sai Luo, Stephen Junkins, Bratin Saha, Ravi Narayanaswamy, Patrick Xi
  • Publication number: 20100122073
    Abstract: A method and apparatus for handling exceptions during execution of a transaction is herein described. A compiler associates a transaction exception handler (TEH) with a transaction in program code, such as through insertion of a call to the TEH. The TEH is also associated with an exception data structure, such as an unwind table, that is utilized during runtime to call an appropriate handler in response to an exception. Additionally, the TEH code is generated by the compiler and inserted into the program code. Upon encountering an exception during execution of the transaction, the TEH is capable of dynamically resizing the transaction to the point of the exception through an attempted commit.
    Type: Application
    Filed: November 10, 2008
    Publication date: May 13, 2010
    Inventors: Ravi Narayanaswamy, Xinmin Tian, Bratin Saha, Ali-Reza Adl-Tabatabai, Robert Geva, Clark Nelson, Sergey Preis, Sergey Kozhukhov, Aleksei G. Cherkasov