Abstract: A method for managing data transfer for a plurality of processors. Transfer messages exchanged between processor units and an external node in an integrity manager located in hardware in communication with the processor units and the external node are received. An exchange of the transfer messages is managed by the processor units with the external node based on a selected mode in mixed integrity modes such that redundantly calculated outputs from the processor units in a high integrity mode match.

Abstract: A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.

Abstract: A method for managing data transfer for a plurality of processors. Transfer messages exchanged between processor units and an external node in an integrity manager located in hardware in communication with the processor units and the external node are received. An exchange of the transfer messages is managed by the processor units with the external node based on a selected mode in mixed integrity modes such that redundantly calculated outputs from the processor units in a high integrity mode match.

Abstract: A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.

Abstract: A differential time domain digital communication bridge module interfaces 100 Mbps Ethernet traffic with a T3 communication link, using a relatively small sized data buffer. To avoid dropping packets, the relatively large sized buffer in the Ethernet switch is used to temporarily store packets, in when an upper threshold of the storage capacity of the buffer is reached. The upper threshold leaves enough storage overhead in the buffer to allow the Ethernet switch to complete its current transmission of a maximum length packet. When a lower threshold is reached a ‘resume transmission’ packet is sent to the switch. The lower threshold provides sufficient buffer space to allow the T3 transmitter to read out the contents of the buffer without underflow.

Abstract: A programmable network-DTE interface integrates T1/E1 framer, data pump and microprocessor components into a common subsystem chip architecture, and interfaces each of these components by means of a user programmable multiplexing subsystem, so as to allow any of the functional blocks of the architecture to be selectively enabled or disabled/by-passed by the user.

Abstract: A bidirectional serial TDM backplane—UTOPIA interface contains an ATM cell boundary location and transmit flow control mechanism, to provide for the efficient capture and storage of ATM cells from a serial TDM channel. Once stored in a transmit buffer, individual ATM cells are controllably read out for application to a downstream UTOPIA interface. In the upstream direction from the UTOPIA bus toward the serial TDM backplane, ATM cells are stored in a multi-cell receive buffer, so that they may be serialized for application to the TDM backplane. In the absence of ATM data cells to transfer, unfilled timeslots are filled with idle cells to maintain the ATM bus active.

Abstract: A programmable network-DTE interface integrates T1/E1 framer, data pump and microprocessor components into a common subsystem chip architecture, and interfaces each of these components by means of a user programmable multiplexing subsystem, so as to allow any of the functional blocks of the architecture to be selectively enabled or disabled/by-passed by the user.

Abstract: A shared T1/E1 signaling bit processor interfaces with either T1 or E1 traffic, and controllably performs robbed bit signal extraction and insertion for T1/E1 signaling protocol using a common set of input/output circuitry and associated decode/control logic therefor. A receiver subsystem controllably samples and extracts signaling bits from selected time slots within serial frames of data incoming from the network to the DTE for delivery to the control processor; a transmitter subsystem controllably inserts signaling bits into selected signaling channels of serial frames of data outgoing from the DTE to the network.

Abstract: A bidirectional serial TDM backplane—UTOPIA interface contains an ATM cell boundary location and transmit flow control mechanism, to provide for the efficient capture and storage of ATM cells from a serial TDM channel. Once stored in a transmit buffer, individual ATM cells are controllably read out for application to a downstream UTOPIA interface. In the upstream direction from the UTOPIA bus toward the serial TDM backplane, ATM cells are stored in a multi-cell receive buffer, so that they may be serialized for application to the TDM backplane. In the absence of ATM data cells to transfer, unfilled timeslots are filled with idle cells to maintain the ATM bus active.