Abstract: A system and method which conserves energy in the operation of a transponder or tag (14) by providing that the transponder (14) be enabled or awakened in multiple stages. A threshold detector (62) is provided which measures the power level of received RF energy. If the RF energy received by the detector (62) exceeds a pre-determined level, the transponder (14) then employs a modulation detector (64) to ascertain whether it has been awakened by a valid interrogation signal from an interrogator (12) or whether the RF energy received was merely a spurious burst of RF energy from some other source. If a pre-determined modulation is detected by the modulation detector (64), the transponder (14) is then fully activated to its normal operational state.

Abstract: A system for automated toll collection which utilizes Global Positioning System technology. The invention includes a Toll Tag 24 which comprises GPS sensor 32, signpost sensor 36, gatekey transmitter 38, and processing & recording module 40. Module 40 is comprised of memory 30 storing known toll location, computer or toll area detector 34, memory for time and location 42, and time clock 44. Once computer 34 determines that a toll area has been entered, it records the entry in memory 42 and activates transmitter 38 to send a signal to sentry receiver 52 which communicates same to toll authority exchange 26.

Abstract: A system and method which conserves energy in the operation of a transponder or tag (14) by providing that the transponder (14) be enabled or awakened in multiple stages. A threshold detector (62) is provided which measures the power level of received RF energy. If the RF energy received by the detector (62) exceeds a pre-determined level, the transponder (14) then employs a modulation detector (64) to ascertain whether it has been awakened by a valid interrogation signal from an interrogator (12) or whether the RF energy received was merely a spurious burst of RF energy from some other source. If a pre-determined modulation is detected by the modulation detector (64), the transponder (14) is then fully activated to its normal operational state.

Abstract: Disclosed is a system and method which protects a transponder or tag (14) from being enabled or awakened by spurious RF energy. A modulation detector (64) is provided which detects a modulation signal that is superimposed upon an RF modulation from an interrogator (12). Preferably this superimposed modulation is of a low frequency, below those typically existing as Electro-Magnetic Interference (EMI), such that the transponder (14) is less likely to be erroneously activated by an unintended RF signal. Upon reception of an RF interrogation having the proper modulation superimposed thereupon, the modulation detector (64) is operable to awaken other circuitry within the transponder (14) such that the transponder (14) is then operable to communicate with the interrogator (12).

Abstract: Airborne navigation and communication systems are disclosed including a VOR/LOC (VHR Omnirange/Localizer) receiver and a communication transceiver each with separate control and display panels. Each panel includes a ten push-button press keys numbered 0-9, a function controller for operating mode selection and general control, a pair of digital displays (5 digits each) for displaying keyboard channel selection including an active channel and a standby channel and additional data, three function press keys--one for switching a standby channel into the active channel or vice versa or resetting the timer or changing the digital bearing display from "TO" to "FROM", a second key for either recalling a channel or backing up to a digit for correction during data entry, and a third key for storing frequency in memory locations or entering data.

Abstract: An auto notch system which automatically "notch" filters up to four interference signals (interferers) in the band from 50 KHz to 150 KHz comprises a signal detector, an adjustable notch filter, a bandpass receiver and a digital controller, plus the software that runs in the digital controller. The signal detector circuit has an antenna, a preamplifier and a group of "fixed" filters. The adjustable notch filters are four circuits, each includes an active notch type filter stage with a DAC (digital to analog converter) in series with the input resistor to allow gain control and another DAC that controls the current through a diode that is optically coupled to a light dependent resistor pair. The light resistor pair is in the filter loop and as the resistance varies the frequency response of the filter changes. Thus the frequency response is controlled by varying the diode current.

Abstract: A communications link having a position capability responsive to either a manual or remote control actuation. In one embodiment, a remote carrier has a navigation system for outputting signals representative of the carrier location or position. A frequency shift key (FSK) modulator is connected to the navigation system for tone coding the carrier position signals, a transmitter of a transceiver is connected to the modulator for transmitting the carrier position signals, and a position enable switch for controlling selectively the transmittal of the carrier position signals.

Abstract: A controlled antenna tuner comprises a power amplifier and a microprocessor, an attenuator connected to the power amplifier for selectively controlling the power output, a low pass filter connected to the power amplifier and microprocessor for channel frequency selection, a vertical standing wave ratio (VSWR) circuit inductively connected to the low pass filters output for determining the VSWR of the antenna, an impedance (magnitude) bridge and a phase detector bridge selectively connected to the low pass filter RF output and to the microprocessor for sensing the tuning status of an antenna, and an LC tuner network connected to the phase detector bridge and microprocessor, the microprocessor processing outputs of the impedance and phase detector bridges into tuning signals for the LC tuner to tune the antenna to the selected channel and storing the tuning signals for the selected channel for future use.

Abstract: Combined keyed AGC and pulse amplitude comparison circuit for use in pulse pair communications system such as DME wherein AGC keying signal is constituted by the second pulse having a predetermined spacing from a first pulse of a pair and wherein said second pulse also provides a reference against which the amplitude of succeeding pulses is compared. Pulses with amplitudes above said reference level are passed to a decoder for determining pulse spacing. The decoder determines which pulse pairs are properly spaced so that the second pulse of a pair can serve as a keying signal.

Abstract: A phase detector which employs four memory elements suitably comprised by D-type flip-flops. The detector provides an output dependent upon the phase difference between two input signals. One pair of memory elements is clocked by one input signal. The other pair of memory elements is clocked by the other input signal. The memory elements are so arranged that when the ratio of the frequencies of the input signals is less than 2:1, the detector provides three output states which may be used in a phase locked oscillator to cause, in the first state, an increase in the frequency of one input signal; in the second state, no frequency change; and in the third state, a decrease in frequency. Above a frequency ratio of 2:1, the detector never enters the second state. Elimination of the second state under such conditions decreases the time required for a phase locked oscillator with this detector to achieve phase lock.

Abstract: A phase lock detector for a digital frequency synthesizer. The frequency synthesizer includes a programmable digital frequency divider for the output signal, a reference frequency Fr oscillator and a phase lock loop which controls the frequency of the synthesizer output by comparing the phase of the frequency divider signal with the phase of the reference signal. The frequency Fr of the synthesizer is determined by programming N in the relationship ##EQU1## The phase lock detector includes logic means providing a "window" which is "open" for a count which is symmetrically less than and more than the factor M. The detector does not signal "out-of-lock" condition as long as output from the programmable divider occurs during the time the detector window is open.