Abstract: A method for authorizing an access to a table of address correspondence between a multitask CPU and at least one memory containing several programs, consisting of calculating, on each task change of the CPU, a signature of at least part of the program instruction lines, and checking the conformity of this signature with a signature recorded upon previous execution of the involved program.

Abstract: A method and an element of ciphering by an integrated processor of data to be stored in a memory, including applying a ciphering algorithm which is a function of a key specific to the integrated circuit and of an initialization vector, and of memorizing at least the ciphered data, the initialization vector depending at least on the address of storage of the data in the memory.

Abstract: A method for recording at least one block of variable data in a first volatile memory external to a microprocessor, including calculating and storing a digital signature taking into account at least partially the address and the content of said data block in the memory, and at least a first random digital value internal to the microprocessor.

Abstract: For the encryption of data to be stored in a memory external to a circuit, provision is made to store in the external memory encrypted data words in association with an initialization vector and a key identifier associated with a secret key that has served to encrypt same.

Abstract: A method and a system for authenticating an electronic tag by a host communicating with this tag via a reader, including: calculating, on the tag side, a first digital signature using at least one first function shared by the tag and the reader, taking into account at least one first secret key known by the electronic tag and the reader only; transmitting the first signature to the reader; calculating, on the reader side, a second digital signal using at least one second function, different from the first function and shared by the reader and the host, taking the first signature into account; transmitting the second signature to the host; and checking, on the host side, the coherence between the second signature and a validation value calculated based on said second function and on a second secret key known by the host and by a single element selected from among the tag and the reader.

Abstract: A method of cyphering, by an integrated processor, of a set of data to be stored in a memory, including performing, in a continuous operation following a data flow, the steps of dividing the data flow into blocks of predetermined size and, for each block: generating a cyphering key using a pseudo-random generator implementing a continuous algorithm of cyphering according to a key specific to the integrated circuit and of an initialization vector changing for each block; combining the data block and the corresponding key in a continuous operation; and storing in the memory each cyphered block and the initialization vector used to cypher it.

Abstract: A method for recording at least one block of variable data in a first volatile memory external to a microprocessor, including calculating and storing a digital signature taking into account at least partially the address and the content of said data block in the memory, and at least a first random digital value internal to the microprocessor.

Abstract: A method and an element of ciphering by an integrated processor of data to be stored in a memory, including applying a ciphering algorithm which is a function of a key specific to the integrated circuit and of an initialization vector, and of memorizing at least the ciphered data, the initialization vector depending at least on the address of storage of the data in the memory.

Abstract: A circuit for controlling the random character of a bit flow, including an input shift register receiving the bit flow and having its outputs exploited in parallel, at least one element for comparing at least a partial content of the input register with predetermined patterns, a plurality of counters in a number at most equal to the number of predetermined patterns, and an element for detecting the exceeding of at least one threshold by one of the counters, the result of this detection conditioning the state of a word or bit indicative of the random or non-random character of the bit flow.

Abstract: For the encryption of data to be stored in a memory external to a circuit, provision is made to store in the external memory encrypted data words in association with an initialization vector and a key identifier associated with a secret key that has served to encrypt same.

Abstract: An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1?(n+2) irreversible counting cells distributed in at least n groups of 2p?1 counting cells, where p designates the group rank, and at least n?1 parity calculators, each calculator providing a bit of rank p, increasing from the most significant bit of the result count, taking into account the states of the cells of the group of same rank.

Abstract: A circuit for controlling the random character of a bit flow, including an input shift register receiving the bit flow and having its outputs exploited in parallel, at least one element for comparing at least a partial content of the input register with predetermined patterns, a plurality of counters in a number at most equal to the number of predetermined patterns, and an element for detecting the exceeding of at least one threshold by one of the counters, the result of this detection conditioning the state of a word or bit indicative of the random or non-random character of the bit flow.

Abstract: A method for authorizing an access to a table of address correspondence between a multitask CPU and at least one memory containing several programs, consisting of calculating, on each task change of the CPU, a signature of at least part of the program instruction lines, and checking the conformity of this signature with a signature recorded upon previous execution of the involved program.

Abstract: An increasing monotonous counter over n bits formed as an integrated circuit, comprising: an assembly of 2n+1−(n+2) irreversible counting cells distributed in at least n groups of 2p−1 counting cells, where p designates the group rank; and at least n−1 parity calculators, each calculator providing a bit of rank p, increasing from the most significant bit of the result count, taking into account the states of the cells of the group of same rank.

Abstract: A method and a system for authenticating an electronic tag by a host communicating with this tag via a reader, consisting of: calculating, on the tag side, a first digital signature by means of at least one first function shared by the tag and the reader, taking into account at least one first secret key known by the electronic tag and the reader only; transmitting the first signature to the reader; calculating, on the reader side, a second digital signal by means of at least one second function, different from the first function and shared by the reader and the host, taking the first signature into account; transmitting the second signature to the host; and checking, on the host side, the coherence between the second signature and a validation value calculated based on said second function and on a second secret key known by the host and by a single element selected from among the tag and the reader.

Abstract: A method of cyphering by an integrated processor of a set of data to be stored in a memory, consisting of performing, in a continuous operation following a data flow, the steps of dividing the data flow into blocks of predetermined size and, for each block: generating a cyphering key by means of a pseudo-random generator implementing a continuous algorithm of cyphering according to a key specific to the integrated circuit and of an initialization vector changing for each block; combining the data block and the corresponding key in a continuous operation; and storing in said memory each cyphered block and the initialization vector used to cypher it.