Abstract: A switching stage includes a differential amplifier configuration. An emitter follower transistor is connected downstream of the differential amplifier configuration. A terminal is provided for a first supply potential. A terminal for a second supply potential is connected to the collector of the emitter follower transistor. A controllable current source is connected between the emitter of the emitter follower transistor and the terminal for the first supply potential. The current source has a control input. A resistor has a first terminal connected to the emitter of the emitter follower transistor and a second terminal connected to a switching stage output. A circuit having a signal output is connected to the first and second terminals of the resistor and to the terminal for the first supply potential, for supplying a signal at the signal output being dependent on the polarity of a voltage dropping at the resistor.

Abstract: A signal level converter for converting CMOS input signal levels to ECL output signal levels includes first and second transistors having emitters connected to each other. The collector of the first transistor is directly connected to a first supply voltage potential. A first resistor is connected between the collector of the second transistor and the first supply voltage potential. The base of the second transistor is connected to a reference potential. A third transistor has a collector connected to the emitters of the first and second transistors. A second resistor is connected between the emitter of the third transistor and a second supply voltage potential. The base of the third transistor is connected to a control potential. A fourth transistor has a collector connected to the first supply voltage potential and a base connected to the collector of the second transistor.

Abstract: An integratable transistor circuit for outputting logical levels includes a switch stage, a switch stage output current amplifier associated with the switch stage, and a level monitoring circuit associated with the switch stage. The switch stage at least includes at least one transistor serving as a switch element and having a primary current path and a control input serving as a switch stage input. At least one resistor is connected to the primary current path of the at least one transistor at a coupling point serving as a switch stage output. The at least one resistor and the primary current path of the at least one transistor form a series circuit having a first end with the at least one resistor connected to a first supply voltage and a second end connected to a second supply voltage. The level monitoring circuit includes at least one control input receiving a reference voltage for determining a switch stage output level.

Abstract: Although known circuit arrangements in NTL technology work just as fast as gates constructed in ECL technology, they have a transmission characteristic that is hardly useful in practice. In the NTL technology of the present disclosure, a transmission characteristic of the gates executed in NTL technology is modified by inserting MOS transistors such that they satisfy respective requirements of a logic circuit arrangement, even in combination with other logic circuit families.

Abstract: A signal level converter for converting digital input signal levels to CML or ECL output signal levels upon an input signal level rise greater than an output signal level rise, includes a load resistor having first and second terminals. A current path is disposed between the first terminal of the load resistor and a first supply voltage potential. The second terminal of the load resistor is connected to a second supply voltage potential for CML or ECL output signal levels to form a digital H level. The first terminal of the load resistor forms a converter output for CML output signal levels and/or a bipolar transistor is connected as an emitter follower having a base electrode connected to the first terminal of the load resistor and an emitter electrode forming a converter output for ECL output signal levels. A current source field transistor is connected in the current path and forms a constant current source.

Abstract: A circuit configuration includes first, second and third current impressing devices. First and second bipolar transistors have coupled emitter terminals being connected through the first current impressing device to a first potential, collector terminals carrying output signals and being connected directly or through respective resistors to a second potential, and base terminals. A first field effect transistor has a gate terminal being acted upon by a first input signal, a drain terminal being connected through a further resistor to the second potential, and a source terminal being connected to the base terminal of the first bipolar transistor and through the second current impressing device to the first potential.

Abstract: A trigger circuit with switching hysteresis includes first, second and third current sources. A first transistor pair is supplied by the first current source and has transistors with coupled emitters, load circuits and input circuits. The input circuit of one of the transistors of the first pair is acted upon by a reference potential and the input circuit of the other of the transistors of the first pair being acted upon by an input signal. Load resistors are each connected in the load circuit of a respective one of the transistors of the first pair. A coupling resistor interconnects the load circuits of the transistors of the first pair. A second transistor pair is supplied by the second current source and has transistors with coupled emitters, load circuits directly coupled with corresponding load circuits of the transistors of the first pair and input circuits cross-coupled with corresponding load circuits of the transistors of the first pair.

Abstract: An ECL-TTL signal level converter includes a first transistor pair having transistors controlled by ECL signals. A second transistor pair is connected to the transistors of the first transistor pair. Collector resistors are connected between the transistors of the second transistor pair and a first supply potential. A third transistor pair has transistors connected to the transistors of the first transistor pair. A fourth transistor pair has transistors connected to the transistors of the first transistor pair and to the transistors of the third transistor pair. A current impressing device is connected between the transistors of the fourth transistor pair and a second supply potential. A push-pull output stage is connected to the transistors of the second transistor pair for the emission of a TTL signal.

Abstract: In an ECL memory array, each bit cell has a neutral state prior to each writing of data into a cell following a read access. A write-read control is provided, having a data input, two outputs for supplying output control signals to write-read transistors and two control inputs for two independent write-read control signals. The two output control signals assuming an upper value, a lower value or a intermediate value in accordance with said two write-read control signals and the data input signal, whereby in a transition from a read access to a write access, the level change of the second write-read control signal changes from high to low prior to the change of the first write-read control signal from low to high, so that said write-read control signals are both high immediately prior to each write access.

Abstract: The invention relates to an integrated logic element constructed in E.sup.2 CL technology. In order to be able to reliably identify the contacting of the collector of a transistor in a differential amplifier at which no output signal is tapped, and which contact may be missing, and identifying the same in a static check, a second emitter is provided at least this transistor and connected to the collector of the other transistor of the differential amplifier.

Abstract: In order to avoid noise pulses which occur at the end of a clock pulse given a low signal level at the output of a clock-controlled flip-flop in ECL technology, an auxiliary current which is small in comparison to the primary current is supplied to a differential amplifier which is in a currentless condition during a clock pulse. As a result, the differential amplifier can be set to the respectively correct switch state before the end of the clock pulse.

Abstract: Given a logic element in ECL or E.sup.2 CL technology whose differential amplifier is driven by way of an emitter follower, a transistor is inserted between the emitter-side terminal of the supply voltage and the constant current source for the feed of the differential amplifier, the additional transistor being controlled by the current through the emitter resistor of the emitter follower transistor. With this structure, the absence of or too low a value of the emitter follower current can be perceived during a static check.

Abstract: In a circuit arrangement constructed in accordance with ECL technology, having an input emitter follower, a differential amplifier and an output emitter follower for the non-inverted output signal, the emitter of the transistor operated as an output emitter follower is connected to the collector of the transistor operated as an input emitter follower. This provides not only an elimination of stray power consumption but, rather, also enables the potential of the output to be increased far above the normal operating level by applying a potential to the input which is positive in comparison to the collector supply potential. Given use of the invention as input stages of programmable logic arrays, the same is of particular advantage in testing such arrays.

Abstract: A programmable logic array, constructed in emitter coupled logic technology, may be tested in its non-programmed condition. Diodes are located between all product terminal lines and first test terminals on the semiconductor chip as they are disposed between all sum term lines and a second test terminal. Furthermore, each input line of the sum matrix is respectively connected by way of a diode to the inverting output of a respective different input amplifier. When the sum matrix exhibits more input lines than there are input amplifiers, the connection is repeated cyclically. In this case, the sum matrix is divided into sub-matrices whose mutually corresponding sum term lines are linked by way of logic elements.

Abstract: A DC-DC converter is described of the blocking oscillator type, for charging a battery from a solar cell. The use of a field effect transistor enables the oscillation to be started by the voltage from a single solar cell, even if the battery is fully exhausted. The overall efficiency of the circuit is improved by the use of the base-emitter junction of the switching transistor of the converter as rectifying element for the battery charging current.