Patents by Inventor Claude Blais

Claude Blais has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100218894
    Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.
    Type: Application
    Filed: May 14, 2010
    Publication date: September 2, 2010
    Inventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla
  • Patent number: 7771541
    Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla
  • Publication number: 20080233755
    Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla
  • Publication number: 20070099346
    Abstract: Methods to reduce or eliminate the bleed out of underfill material. Surface treatments to selective areas on a chip carrier substrate surface create a non-wettable surface or a reduced wettability surface in the areas where the underfill should not flow. The substrate surface is subjected to surface treatments such as media blasting or chemical exposure which will roughen the exposed surface.
    Type: Application
    Filed: November 1, 2005
    Publication date: May 3, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta Farooq, Thomas Lombardi, Julie Nadeau Filtreau, Scott Bradley, Claude Blais, Richard Indyk
  • Patent number: 6904673
    Abstract: Ink jet printing apparatus is employed to form a non-polar ink stop line around a chip site on the polar surface of an organic laminate substrate. The non-polar ink stop line acts to confine polar liquid flux from spreading after application of the flux to the chip site prior to chip joining. Excessive flux spreading results in insufficient flux being present at the chip site for the formation of good electrical connections during solder reflow upon chip joining.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: Claude Blais, Julie Nadeau Filteau, Pierre M. Langevin, Robert L. Toutant, Alain Warren
  • Patent number: 6112976
    Abstract: The disclosed invention provides for a method of manufacturing solder columns for particular use in attaching substrates to a printed circuit board. The method results in columns of homogeneous composition and thus overcomes problems associated with the phenomena of segregation. The method includes the steps of forming particles of the metal composition to be used for the columns from a molten source of the composition. The solid particles are then formed into segments of homogeneous composition by drawing ingots of the composition into wire and severing the wire into segments.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: September 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Louis-Marie Achard, Claude Blais, David Hirsch Danovitch, Jean-Francois Garneau, Michel Robert
  • Patent number: 5457299
    Abstract: A method for encapsulating a semiconductor chip. The method includes the steps of first positioning a chip over a laser-curing cavity, and then dispensing a predetermined amount of encapsulant over the chip. Sequential steps include synchronizing a firing of a laser pulse immediately after the dispensing step, and curing the encapsulant by conducting heat generated by the laser pulse, through the chip.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: October 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: Claude Blais, Pedro A. Chalco