Patents by Inventor Claude E. P. Chapron

Claude E. P. Chapron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5017997
    Abstract: The invention relates to an integrated circuit having a transistor suitable for integrated injection logic (I.sup.2 L) with a single collector output region and having at least one base contact disposed between the collector output region (C.sub.60, C'.sub.60) and the injector (IN.sub.6), the surface of the collector output region being several times larger than that of a logic gate of the I.sup.2 L multi-collector type. The base (B.sub.60) has at least two rows of interconnected contacts: a first row (CB.sub.60, CB.sub.61, CB.sub.62) constituting the base contact disposed between the collector and the injector, and at least a second row (CB.sub.63, CB.sub.64, CB.sub.65) situated at the perimeter of the collector (C.sub.60,C'.sub.60), which can consist of one or several parts. The injector (IN.sub.6) may also have a row of interconnected contacts (CIN.sub.1, CIN.sub.2, CIN.sub.3).
    Type: Grant
    Filed: December 1, 1989
    Date of Patent: May 21, 1991
    Assignee: U.S. Philips Corp.
    Inventors: Claude E. P. Chapron, Jean B. Parpaleix
  • Patent number: 4903095
    Abstract: The protection device according to the invention is of the type comprising three active regions of alternating conductivity types, whose extreme regions are connected on the one hand to an input to be protected and on the other hand to a supply voltage source of the circuit.The first active region (2) forms a strip surrounded by the second active region (3). Contact regions (6 and 7) cover the active regions (2 and 3, respectively) and are covered by metallizations (8 and 9), respectively). The contact regions (6 and 7) are separated by thick insulating regions (4). One of the metallizations (8) is connected to the input to be protected and the other metallization (9) is connected to a reference voltage source.
    Type: Grant
    Filed: August 10, 1988
    Date of Patent: February 20, 1990
    Assignee: U.S. Philips Corporation
    Inventor: Claude E. P. Chapron
  • Patent number: 4749442
    Abstract: In the method according to the invention conductive electrodes are provided with the aid of a mask aligned with respect to at least two contact windows present in an insulating layer. First, layers of metal combining with semiconductor material, for example, Pt silicide, are provided in the contact windows. A narrow region of the insulating layer between the two contact windows may have a reduced dimension because in their extreme relative positions the conductive electrodes can only partially cover the contact windows. The invention also relates to semiconductor devices comprising logic (or low-noise) transistors, or transistors for very high frequencies whose structure is improved with respect to their dimensions, their series resistance value and/or their gain.
    Type: Grant
    Filed: March 18, 1986
    Date of Patent: June 7, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Stefan Barbu, Claude E. P. Chapron