Abstract: A synchronization device for digital data frame transmission system comprising an n bit series register transferring its contents at the line frequency to a parallel register also of n bits. The m first bits of the series register are also directed to a logic circuit which tests their conformity with the beginning of the synchronization word. When there is conformity, the logic circuit controls a divider dividing by n which controls, in its turn, at the line frequency divided by n, the transfer of the contents of the parallel register to a PROM memory. The purpose of the PROM is to recognize the entire synchronization word. When there is no recognition, the operation of the divide by n divider is inhibited and the procedure begins again.

Abstract: A process and system are provided for transmitting additional information, called order track, superimposed on the information to be transmitted, by alteration of the coding law. The process involves:detection of at least one possible value of the information to be transmitted, for which the coding law is altered depending on the order track information.The first coding is transformed into a second coding by choice of one of several alphabets capable of ensuring such a transformation, this choice being effected depending on the value of the current numerical sum, in accordance with the coding law such that the value of this numerical sum is minimized.the output at one end of the transmission channel of the information is expressed in the second coding as altered by the order track.The information received at the other end of the transmission channel is transformed into information expressed in the first coding.The order track is detected by detection of the alteration in the coding law.

Abstract: Apparatus for regenerating periodic clock signals in a ternary pulse transmission system. It comprises an input transformer with a secondary winding having a grounded midpoint, a high "Q" band-pass filter tuned to the repetition frequency of the clock signals, and a shaping circuit for these clock signals. The apparatus further comprises a threshold level comparator differentially supplied by the input transformer and supplying through an addition circuit an adjustable delay line whose output is connected through the filter to the said shaping circuit. The latter circuit may comprise a limiting amplifier combined with a pair of flip-flop circuits.