Abstract: A circuit for calculating the discrete Fourier transform which includes a multiplier, two adders for effecting the calculation of the discrete Fourier transform while describing a butterfly data path, and address processors which supply the multiplier and adders with continuous data under the control of a synchronization clock. To accelerate the calculations, the processor has a memory for reducing the data access time. This memory is divided into two parts, each of which alternately plays the role of calculation memory and input/output memory for the transfer of data with a memory external to the processor.