Abstract: ATM path switched ring switching is based on a ring segment BIP. An ATM VP ring segment is defined as originating at an ATM VP ring input and terminating at an ATM VP ring output. A ring segment BIP is composed of the path BIP error counts of multiple SONET/SDH paths from the ring segment input to the ring segment output.

Abstract: ATM path switched ring switching is based on a ring segment BIP. An ATM VP ring segment is defined as originating at an ATM VP ring input and terminating at an ATM VP ring output. A ring segment BIP is composed of the path BIP error counts of multiple SONET/SDH paths from the ring segment input to the ring segment output.

Abstract: ATM path switched ring switching is based on a ring segment BIP. An ATM VP ring segment is defined as originating at an ATM VP ring input and terminating at an ATM VP ring output. A ring segment BIP is composed of the path BIP error counts of multiple SONET/SDH paths from the ring segment input to the ring segment output.

Abstract: A VT group optical extension format (FIGS. 7 and 8) defines a transport frame for the transfer of 135 bytes, each byte comprising 8 bits, the format providing a line rate of 8.640 Mbit/S. Each frame comprises a transport overhead portion and a payload portion. The transport overhead portion is comprised of 27 bytes and defines various operations, administration and maintenance functions, whereas the payload portion is comprised of 108 bytes which directly correspond to one VT group of an STS-N frame (FIG. 1). The VT group optical extension format line rate is determined as an integer multiple (i) of an STS-N network element clock where i is 6 if N is 1 and i is 18 if N is 3.

Abstract: A local area network interface for a network element having redundant processors is made by using a pair of connectors for each processor. A delay line is used between pairs of connectors for non-redundant LAN configurations. For redundant LANs, the delay line is not used.

Abstract: A SONET virtual tributary reformatter has a drop encoder that receives incoming data of a second VT size mapped according to first VT size and provides the data in a format designed for the first VT size and also has an add decoder that receives outgoing data signals of the second VT size in the format of the first VT size and provides the outgoing data of the second VT size mapped according to the first VT size.

Abstract: A line unit, used in a line shelf having a line shelf processor and common logic, is provided with an EEPROM device for storing information relative to the line unit. The stored information includes line unit type identification codes, auto provisioning data, gain and equalization adjustment data and signaling translation tables. The data contained within the EEPROM may be utilized by the line shelf processor to provide automatic initialization and provisioning of the line unit when first inserted into the line shelf, and automatic signaling translation so that line unit signaling becomes compatible with a transmission facility connected to the line shelf. The need for factory preset resistors installed in the line unit may be eliminated by storing within the EEPROM a required gain setting.

Abstract: A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Abstract: A terminal for a telecommunications system provides access to one or two high-speed synchronous transmission lines by both low-speed transmission lines and subscriber lines. A core module includes interfaces to the high-speed lines, a time slot interchanger, an interface to the low-speed transmission lines, processors and overhead circuitry for supporting the terminal. An access module includes a plurality of line shelves connected to subscriber lines, each line shelf includes a pair of processors and for time slot assignors. A multi-link serial bus connects the time slot interchanger to the access module and to the low-speed interface and provides close coupling between the processors in the core module and the line shelves. The processors cooperate to groom subscriber information from said subscriber lines to and from time slots in said high-speed feeder line and said low-speed transmission line.

Abstract: A serial transport frame format is described which transfers data between two locations. The serial transport frame format comprises a fixed number of channels per frame, each channel having a predetermined size. One channel per frame contains frame synchronization information and each channel which conveys data, contains a first portion for the transfer of data and a second portion which contains associated control information.