Patents by Inventor Claude R. Bertin

Claude R. Bertin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Merged array PLA device, circuit, fabrication method and testing technique
    Patent number: 4212026
    Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs and OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array.
    Type: Grant
    Filed: September 25, 1978
    Date of Patent: July 8, 1980
    Assignee: International Business Machines Corporation
    Inventors: P. S. Balasubramanian, Claude R. Bertin, Stephen B. Greenspan
  • Merged array PLA device, circuit, fabrication method and testing technique
    Patent number: 4140967
    Abstract: A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array.
    Type: Grant
    Filed: June 24, 1977
    Date of Patent: February 20, 1979
    Assignee: International Business Machines Corporation
    Inventors: Peruvemba S. Balasubramanian, Claude R. Bertin, Stephen B. Greenspan