Abstract: The invention relates to a dipole antenna including first and second radiating elements electrically connected via a transition, said first and second elements being associated with a frequency f1 in a frequency band, a feeding point the feeding point and the reference point being respectively connected to a feeding conductor and a ground conductor of a feeding line, and a balun. The balun is formed by a slot arranged in the first radiating element, said slot having a short circuit at a first end and an open circuit at a second end next to the transition. The feeding point and the reference point are arranged on opposite sides of the slot.

Abstract: The invention relates to a dipole antenna including first and second radiating elements electrically connected via a transition, said first and second elements being associated with a frequency f1 in a frequency band, a feeding point the feeding point and the reference point being respectively connected to a feeding conductor and a ground conductor of a feeding line, and a balun. The balun is formed by a slot arranged in the first radiating element, said slot having a short circuit at a first end and an open circuit at a second end next to the transition. The feeding point and the reference point are arranged on opposite sides of the slot.

Abstract: The invention relates to a circuit and a method for pairing decoders enabling, with the use of a switch controlled by a processor, to create a communication link successively between a master decoder and each of the slave decoders, without any particular addressing, or cascaded filters.

Abstract: The invention relates to a receiver 1 of signals and proposes to remedy a non-linearity problem in an amplifier 70 of an integrated tuner 7.A linearity compensation circuit 8 is inserted upline from the tuner 7.The compensation circuit 8 presents a characteristic that is the inverse of the characteristic of the low-noise amplifier 708 in order to compensate for the linearity defect.

Abstract: For testing of the appliance, a test adapter is used as an interface, which is inserted into the smart card reader of the appliance. Advantageously, a contact of the smart card reader is used for testing of the appliance, which is not used by the appliance, when operating with a smart card. One of the contacts used for testing of the appliance is in particularly the contact for the programming voltage VPP according to the ISO/IEC 7816-3:1997(E) standard. In a preferred embodiment, the test adapter comprises a serial adapter interface to a RS232 plug, which is coupled to a computer for testing of the appliance. This allows to use the XON/XOFF protocol via two data lines for testing of the appliance. The electronics part of the test adapter is powered via the smart card reader interface, when the test adapter is inserted into the smart card reader of the appliance. The appliance is especially a set-top box or a digital satellite receiver.

Abstract: The invention relates to a circuit and a method for pairing decoders enabling, with the use of a switch controlled by a processor, to create a communication link successively between a master decoder and each of the slave decoders, without any particular addressing, or cascaded filters.

Abstract: The device, and a respective system, comprises a microcontroller for signal processing and an interface controller for communicating with an IC card, the interface controller being coupled between the microcontroller and the IC card. According to the invention, the device comprises a reset button for resetting the microcontroller in case of a malfunction, the reset button being accessible to a customer, and a reset signal from the reset button simulates an IC card extraction or a card supply voltage shut down. In a special embodiment, the reset signal from the reset button is applied to the microcontroller and to the interface controller, and the signal from the reset button resetting the microcontroller is delayed by a delay circuit with respect to the signal, which resets the interface controller. The signal from the reset button is advantageously combined with the signal from a card presence contact via a logical OR-combination, and then coupled to a card presence input of the interface controller.

Abstract: For testing of the appliance, a test adapter is used as an interface, which is inserted into the smart card reader of the appliance. Advantageously, a contact of the smart card reader is used for testing of the appliance, which is not used by the appliance, when operating with a smart card. One of the contacts used for testing of the appliance is in particularly the contact for the programming voltage VPP according to the ISO/IEC 7816-3:1997(E) standard. In a preferred embodiment, the test adapter comprises a serial adapter interface to a RS232 plug, which is coupled to a computer for testing of the appliance. This allows to use the XON/XOFF protocol via two data lines for testing of the appliance. The electronics part of the test adapter is powered via the smart card reader interface, when the test adapter is inserted into the smart card reader of the appliance. The appliance is especially a set-top box or a digital satellite receiver.

Abstract: The invention relates to a receiver 1 of signals and proposes to remedy a non-linearity problem in an amplifier 70 of an integrated tuner 7. A linearity compensation circuit 8 is inserted upline from the tuner 7. The compensation circuit 8 presents a characteristic that is the inverse of the characteristic of the low-noise amplifier 708 in order to compensate for the linearity defect.

Abstract: The present invention relates to a device and a process for the stamping in real time by means of a stamping clock (2) of programs, as well as to a receiver and a broadcasting system containing such a device and a packet string obtained by such a process.

Abstract: The device, and a respective system, comprises a microcontroller for signal processing and an interface controller for communicating with an IC card, the interface controller being coupled between the microcontroller and the IC card. According to the invention, the device comprises a reset button for resetting the microcontroller in case of a malfunction, the reset button being accessible to a customer, and a reset signal from the reset button simulates an IC card extraction or a card supply voltage shut down. In a special embodiment, the reset signal from the reset button is applied to the microcontroller and to the interface controller, and the signal from the reset button resetting the microcontroller is delayed by a delay circuit with respect to the signal, which resets the interface controller. The signal from the reset button is advantageously combined with the signal from a card presence contact via a logical OR-combination, and then coupled to a card presence input of the interface controller.

Abstract: The disclosure relates to a method of synchronization of clocks wherein, in a system including a digital decoder of a receiver equipped with a sampling clock and a digital encoder of an transmitter also equipped with a sampling clock, said method includes the following stages: in the transmitter, coding by packets of samples of a signal by time intervals of predetermined duration and triggering of the transmission of a data frame when a packet of data is ready to be sent; in the receiver, detection of start of said frame, and generation of a reference signal following said detection, said reference signal being used to correct the clock of the receiver.

Abstract: A method of automatically controlling a loop comprising the steps of applying an input signal and an error correction signal to a signal correction circuit to provide a digital corrected signal. Applying the digital corrected signal and a reference signal to an error measurement circuit and providing a difference signal representative of the difference between the corrected signal and the reference signal. Applying the difference signal to a tri-state buffer having an output which is switchable to high impedance and passing the error correction signal to a correction circuit through an integrator and a local generator circuit. The buffer is switched to high impedance when the difference between the error correction signal and the reference signal is zero.