Abstract: A synchronization circuit for use in a bridge connecting an emitter bus operating on an emitter clock frequency to a receiver bus operating on a receiver clock frequency is provided. The synchronization circuit is responsive to a control signal generated by memory status means coupled to a memory which temporarily stores data transmitted from the emitter bus to the receiver bus. The control signal representative of the status of the memory is reflecting asynchronous read and write operations within the memory. The resultant signal output from the synchronization circuit is a one clock synchronized signal such that rising and falling transitions are synchronized to the receiver bus clock frequency.