Abstract: A method and apparatus is disclosed for performing a multi-equalization of a transmitted signal on a channel having varying characteristics comprising equalizing the transmitted signal using a plurality of setting defining a plurality of equalizing functions to provide a corresponding plurality of symbol signal, synchronizing each of the plurality of symbol signals to provide a plurality of synchronized signals, selecting at least one of the plurality of synchronized signals according to at least one transmission performance criterion and providing the selected one of the plurality of synchronized signals.

Abstract: A method and apparatus is disclosed for testing a reconfigurable logic block. Preferably, this invention is intended to be used with Field Programmable Gate Array. According to the invention, a test bus addressing unit and a test bus activation unit are used to perform a test on a logic block. Upon selection of a corresponding logic block, a test data is outputted on a test bus which enables a testing of the logic function.

Abstract: A digital parallelized Infinite Impulse Response (IIR) integrator filter comprising a first channel having a first input and second channel having a second input, a first adder to add the two channel inputs, an integrator to integrate the added channel inputs to provide a first channel output is described herein. The second input channel is adjacent in time to the first channel input. The second channel further comprises a second adder which adds the first output with the second channel input in order to produce a second output, adjacent in time with the first output. This configuration can be generalized to n inputs and m outputs.

Abstract: A system and method for testing the data propagation time in an integrated circuit at relatively low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circuits are provided with at least one inverter for sensing the feeding current of each circuit so as to obtain current pulses that are transformed into binary signals forwarded to a tester that measures the delay time between these signals.

Abstract: A reticle and method simultaneously generate small- and large-scale circuit structures of a parallel processing system. The reticle includes at least two circuit traces having respective contact pads within an overlap zone of the reticle. Connectivity between a circuit trace of one reticle image with a circuit trace of an adjacent reticle image is controlled by varying the degree of overlap between the two images.

Abstract: A synchronous clocking method and apparatus is disclosed for clocking a plurality of processing units. Each of the plurality of processing units is connected to at least another one using an interblock synchronization signal. Upon receipt of the interblock synchronization signal, data is provided between at least two processing units.

Abstract: A method and apparatus is disclosed for testing a reconfigurable logic block. Preferably, this invention is intended to be used with Field Programmable Gate Array. According to the invention, a test bus addressing unit and a test bus activation unit are used to perform a test on a logic block. Upon selection of a corresponding logic block, a test data is outputted on a test bus which enables a testing of the logic function.

Abstract: A parallelized Finite Impulse Response (FIR) is described. The apparatus comprises a structure that may be used to create an integrator filter. The integrator filter may have n inputs and m outputs.

Abstract: A system for Vddq integrated circuit (IC) testing is described herein. The systems teaches the positioning of a resistive element between a voltage source and the power supply terminal of the IC under test and the approximation of the voltage value at the power supply terminal when the IC is generally in a steady state. Depending on the approximated voltage value, the IC under test may be determined faulty or not.

Abstract: A method for decoding a compressed image stream, the image stream having a plurality of frames, each frame consisting of a merged image including pixels from a left image and pixels from a right image. The method involves the steps of receiving each merged image; changing a clock domain from the original input signal to an internal domain; for each merged image, placing at least two adjacent pixels into an input buffer and interpolating an intermediate pixel, for forming a reconstructed left frame and a reconstructed right frame according to provenance of the adjacent pixels; and reconstructing a stereoscopic image stream from the left and right image frames. The invention also teaches a system for decoding a compressed image stream.

Abstract: A reticle and method simultaneously generate small- and large-scale circuit structures of a parallel processing system. The reticle includes at least two circuit traces having respective contact pads within an overlap zone of the reticle. Connectivity between a circuit trace of one reticle image with a circuit trace of an adjacent reticle image is controlled by varying the degree of overlap between the two images.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In one such method, a plurality of sets of input signals is received, and a plurality of sets of corresponding output signals is transmitted. One set of the output signals is delayed with respect to another set by a delay period T_DLY. In another such method, the output signals are transmitted and received on the same semiconductor substrate.

Abstract: A system and method for testing the data propagation time in an integrated circuit at relatively low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circuits are provided with at least one inverter for sensing the feeding current of each circuit so as to obtain current pulses that are transformed into binary signals forwarded to a tester that measures the delay time between these signals.

Abstract: A system for Vddq integrated circuit (IC) testing is described herein. The systems teaches the positioning of a resistive element between a voltage source and the power supply terminal of the IC under test and the approximation of the voltage value at the power supply terminal when the IC is generally in a steady state. Depending on the approximated voltage value, the IC under test may be determined faulty or not.

Abstract: The method is for correcting and decoding a sequence of branches representing encoded data bits into estimated information bits. The encoded data bits were previously encoded in a convolutional manner with v encoded symbols forming a branch where v is a predetermined value.