Abstract: A memory including several modules with each module receiving at the input requests coming from a processor and furnishing at the output the responses to these requests. The requests are transmitted to the input of each module via an input shift register. The responses coming from a module are transmitted to the input of a processor via an output shift register. The number of stages of the input shift register is different for each of the modules and the total number of stages for the input and output shift registers associated with one of the modules is constant and independent of the module in question.

Abstract: A central unit for a data-processing system having a high degree of parallelism. This central unit includes a number of basic processors sending requests to a number of modules in receiving responses from those modules. To simplify the interconnection between the modules and the processors when their number increases, the invention is characterized wherein the requests sent from each processor are transmitted to the input of each of said modules via an input shift register, wherein the response coming from each of the said modules are transmitted to the input of each processor via an output shift register, wherein for any provided processor, the number of stages of said input shift register making it possible to access the modules is different for each of the modules and wherein for any processor, the total number of stages belonging to the input and output shift registers associated with one of the said modules is constant and independent of the module and processor in question.

Abstract: A method of recording numerical information in a plurality of disk units, in which the bits of each word of numerical information are transmitted simultaneously, each bit being allocated to a unit associated with the weight of that bit in that word, and a memory system for implementing the method, including a main controller (2) provided with a selector enabling the distribution and synchronization of the information signals.

Abstract: A method of recording numerical information in a plurality of disk units, in which the bits of each word of numerical information are transmitted simultaneously, each bit being allocated to a unit associated with the weight of that bit in that word, and a memory system for implementing the method, including a main controller (2) provided with a selector enabling the distribution and synchronization of the information signals.

Abstract: A parallel processor having a large number of elementary processors connected in parallel to an address bus and a control bus. Each elementary processor contains a memory and control and processing circuits to perform calculations on bits addressed in the memory and bits coming either from this memory or from a peripheral unit. Each elementary processor further contains a small capacity fast memory and the control and processing circuit contains a single storage flip-flop able to perform calculations in series on the bits extracted from the memories and/or coming from the peripheral unit. All the fast memories are parallel connected.

Abstract: This encoder comprises a series of resistors for determining the reference voltages, and comparators having at least one pair of outputs A and B. First inputs of said comparators are connected respectively to said resistors and second inputs of said comparators are connected to the voltage to be encoded through an impedance adaptor stage. The outputs A and B of the pairs of outputs of each comparator are respectively connected to the outputs B and A of the following comparator and constitute first and second output groups. The first and second groups are connected respectively to the inputs of a comparator constituting a bit of smallest weight of the encoder and the outputs A and B of the other pairs of outputs are connected in a similar manner to comparators constituting bits of greatest weight.