Patents by Inventor Claude Vergnolle

Claude Vergnolle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5283851
    Abstract: The strip is designed to optically interconnect a set of printed circuit boards mounted in a housing. It comprises:a U-section (29) lying alongside and against the edge of the set of printed circuit boards with its back (30) turned towards the printed circuit boards and including two lateral flanges, the back containing apertures (39, . . . , 44) drilled at the same pitch as the spacing of the printed circuit boards andoptical fibers (37, 38) laid in the section (29), running from one aperture (39, . . . , 44) to another, each aperture (39, . . . , 44) drilled in the back (30) of the said section (29) and containing one or several optical fiber (37, 38) ends lying opposite an optical half-connector mounted on the edge of one of the printed circuit boards.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: February 1, 1994
    Assignee: Thomson-CSF
    Inventor: Claude Vergnolle
  • Patent number: 5262351
    Abstract: The invention is a method of producing a multilayer polymer-metal system to interconnect integrated circuits which allows two-dimensional electrical and/or optical connections between components, in which a first layer of polymer is deposited on a rigid substrate such that the layer can be separated from the substrate, in which a multilayer interconnection system is then produced on this first layer using industrial methods and in which the rigid substrate is removed after installation and connection of the integrated circuit.
    Type: Grant
    Filed: July 23, 1991
    Date of Patent: November 16, 1993
    Assignee: Thomson-CSF
    Inventors: Jean-Marc Bureau, Francois Bernard, Dominique Broussoux, Claude Vergnolle
  • Patent number: 4216444
    Abstract: A step adjustable attenuator comprising a silicon substrate on one face of which are deposited thin film-type resistors and electrical conductors by which the resistors are interconnected. Contact points are arranged at the periphery of the substrate and connected to the resistors. However, the attenuating sections are not interconnected on the substrate. A conductive pattern prepared from a conductive film forms finger-like leads of which inner portions are bonded to the contact points. By its shape, the pattern ensures the interconnections between the sections and forms two rows of outputs, one for the connections on the printed-circuit board on which is implanted the attenuator and the other being associated with displaceable straps enabling attenuation to be adjusted.
    Type: Grant
    Filed: September 14, 1978
    Date of Patent: August 5, 1980
    Assignee: Thomson-CSF
    Inventors: Claude Vergnolle, Christian Val
  • Patent number: 4005467
    Abstract: A field-effect transistor designed for high-power operation has a P.sup.+ substrate, preferably of gallium arsenide, topped by an N layer which in turn is covered by a much thinner N.sup.+ film, the layer and film being bisected by a serpentine trench so as to form a pair of interdigitated comb-shaped N.sup.+ segments overlain by metallic deposits which constitute a source and a drain electrode. The trench, advantageously produced by ion bombardment which also has a passivating effect on the surface areas thus exposed, cuts deep enough into the N layer to leave a channel whose conductivity is controlled by a gate electrode substantially coextensive therewith on the opposite substrate face. The prismatic substrate body is peripherally bounded by a mesa flank which may be passivated by a deposit of low-melting glass.
    Type: Grant
    Filed: August 22, 1975
    Date of Patent: January 25, 1977
    Assignee: Thomson-CSF
    Inventor: Claude Vergnolle