Abstract: Mechanisms for communicating with a network adapter using a queue data structure are provided. A device driver invokes device driver services for initializing address translation and protection table (ATPT) entries in a root complex for the queue data structure. The device driver services return untranslated addresses to the device driver which are in turn provided to the network adapter. In response to retrieving a queue element from the queue data structure, the network adapter may request a translation of an untranslated address specified in the queue element and store the translated address in the network adapter prior to receiving a data packet targeting a buffer associated with the queue element.

Abstract: A mechanism for initializing shared memories for sharing endpoints across a plurality of root complexes is provided. A multi-root PCIe manager (MR-PCIM) initializes the shared memory between root complexes and endpoints by discovering the PCIe switch fabric by traversing all the links accessible through the interconnected switches of the PCIe switch fabric. As the links are traversed, the MR-PCIM compares information obtained for each of the root complexes and endpoints to determine which endpoints and root complexes reside on the same blade. A virtual PCIe tree data structure is then generated that ties the endpoints available on the PCIe switch fabric to each root complex. The MR-PCIM, or a single-root PCIe manager (SR-PCIM), may then assign each endpoint and root complex a base and limit within the PCIe memory address space the endpoint belongs to.

Abstract: A computing system is provided with real-time capabilities so that the system is capable of running applications such that one or more real-time criteria are satisfied. An interrupt architecture of the computing system is disabled. The interrupt architecture generates interrupts sent to a firmware of the computing system in response to events. A different architecture is substituted within the computing system for the interrupt architecture. The different architecture is responsive to the events without violating the real-time criteria. In response to the events occurring, the different architecture causes one or more corrective actions to be performed.

Abstract: Mechanisms for communication between host systems using a socket connection and shared memories are provided. With such socket-based communication, a work queue in the host systems may be used to listen for incoming socket initialization requests. A first host system that wishes to establish a socket communication connection with a second host system may generate a socket initialization request work queue element in its work queue and may inform the second host system that the socket initialization request work queue element is available for processing. The second host system may then accept or deny the request. If the second host system accepts the request, it returns the second half of the socket's parameters for use by the first host system in performing socket based communications between the first and second host systems.

Abstract: Mechanisms for migration of single root stateless virtual functions are provided. A Single-Root PCI Configuration Manager (SR-PCIM) provides a system image (SI) with possible virtual function (VF) migration scenarios supported by the endpoint (EP). The SR-PCIM may be instructed that a stateless migration of a VF and its associated application(s) from one SI to another is required. Outstanding requests to the VF are completed and any applications associated with the VF are removed from the SI and the VF is detached from its associated physical function (PF). The SWI may then attach the VF to a target PF which may be in the same or a different EP. The SWI makes the VF available to the SI with which the VF is now associated and the SI configures the VF thereby making it available for use by associated applications.

Abstract: A method mechanism is provided for communication between host systems using a transaction protocol and shared memories. Shared memories are initialized based on a discovery process in a communication fabric such that at least one endpoint has address ranges in shared memories of at least two host systems. A transaction oriented protocol may be established for using the shared memories of the host systems to communicate between root complexes and endpoints of the same or different host systems. The transaction oriented protocol specifies a series of transactions to be performed by the various elements, e.g., root complex or endpoint, to push or pull data. Various combinations of push and pull transactions may be utilized.

Abstract: Mechanisms for hot-plug/remove of a new component in a running communication fabric, such as a PCIe fabric, are provided. With these mechanisms, the addition of a new component in the fabric is detected and an event is sent to a multiple root fabric configuration manager. The multiple root fabric configuration manager gathers information about the new component and updates its I/O component tree structure in its configuration data structure to include the new component. The new component may then be utilized via the updated configuration data structure. When a component is to be removed, the multiple root fabric configuration manager receives an event indicating the component to be removed, determines which branches of the tree structure are affected by the removal, and updates its configuration data structure accordingly to remove the component and its associated components from the virtual plane of the removed component.

Abstract: A mechanism is provided for communication between host systems using a queuing system and shared memories. Memory address spaces of the host systems are initialized such that endpoints may be accessible by root complexes across host systems. These memory address spaces may then be used to allow system images, and their corresponding applications, associated with these root complexes to communicate with the endpoints using a queuing system. Such a queuing system may comprise queue structures having doorbell structures for providing information about the queue entries in the queue structures. Queue elements may be generated and added to the queue structures, and the doorbell structure may be written to, in order to thereby inform an endpoint or root complex that queue elements are available for processing. DMA operations may be performed to retrieve the queue elements and the data corresponding to the queue elements.

Abstract: Mechanisms for migration of a virtual endpoint from one virtual plane to another are provided. With these mechanisms, when a management application requests migration of a virtual endpoint (VE) from one virtual plane (VP) to another, a fabric manager provides an input/output virtualization intermediary (IOVI) with an interrupt to perform a stateless migration. The IOVI quiesces outstanding requests to the virtual functions (VFs) of the VE, causes a function level reset of the VFs, deconfigures addresses in intermediary switches corresponding to the VP, and informs the fabric manager that a destination migration is requested. The fabric manager sends an interrupt to the destination IOVI which performs a function level reset of the destination VFs and reprograms the intermediary switches with the addresses of the destination VP. The destination VFs may then be placed in an active state.

Abstract: Mechanisms for migration stateless virtual functions from one virtual plane to another are provided. When a migration of a source virtual function to a destination virtual function in another virtual plane is to be performed, a source single root PCI manager (SR-PCIM) is first interrupted by a multiple root PCI manager (MR-PCIM). Configuration information that defines the source virtual function is then redefined on the destination virtual function for this stateless migration. A function level reset may then be performed on the source virtual function. The destination SR-PCIM may be interrupted by the MR-PCIM with an interrupt for the destination virtual function. A function level reset may then be performed on the destination virtual function. The destination virtual function state may then be changed to an “active” state such that the migrated virtual function begins processing transactions.

Abstract: Mechanisms for splitting responsibilities for communicating with an endpoint between a device driver and device driver services are provided. With these mechanisms, the device driver is responsible for managing queues for communicating requests between applications in a logical partition and the endpoint. The device driver further invokes memory management via device driver services. The device driver services are responsible for managing memory accessible by the endpoint, including the address translation and protection table (ATPT) or a root complex and the address translation caches (ATCs) of the endpoint. The device driver services may associate untranslated addresses for data structures used to communicate between a system image and the endpoint. The endpoint may request translations of the untranslated addresses and may cache the translations in the ATCs.

Abstract: Mechanisms for communicating with an I/O device or endpoint using a queue data structure and pre-translated addresses associated with the queue data structure are provided. With the mechanisms, a device driver invokes device driver services for initializing address translation and protection table (ATPT) entries in a root complex for the queue data structure. The device driver services return untranslated addresses to the device driver which are in turn provided to the I/O device or endpoint. The I/O device or endpoint may then request a translation of these untranslated addresses and store them in the I/O device or endpoint prior to receiving an I/O operation targeting the queue data structure. The cached translation may be used to directly access the queue data structure from the I/O device or endpoint by bypassing the root complex's address translation facilities.

Abstract: Mechanisms for communicating with a memory registration enabled adapter, such as an InfiniBand™ host channel adapter, are provided. With the mechanisms, device driver services may be invoked by a device driver for initializing address translation entries in an address translation data structure of a root complex. An address of a device driver data buffer data structure and registration modifiers may be passed by the device driver to the device driver services. The device driver services may create address translation data structure entries in the address translation data structure associated with the root complex and memory registration (MR) address translation entries in a MR address translation data structure of the adapter. The MR address translation data structure may then be used with I/O operations to bypass the address translation data structure associated with the root complex.

Abstract: A computing system is provided with real-time capabilities so that the system is capable of running applications such that one or more real-time criteria are satisfied. An interrupt architecture of the computing system is disabled. The interrupt architecture generates interrupts sent to a firmware of the computing system in response to events. A different architecture is substituted within the computing system for the interrupt architecture. The different architecture is responsive to the events without violating the real-time criteria. In response to the events occurring, the different architecture causes one or more corrective actions to be performed.

Abstract: A system and method for registering combinations of physical and/or virtual functions for configuring an endpoint are provided. With the system and method, a mechanism informs a management component of a multifunction endpoint's functional combinations. The management component may then use this information to select the functional combinations that are to be made visible to each system image. The informing of the management component may be performed by writing values to various predefined fields in a configuration space for a physical or virtual function that provides information regarding the number of virtual functions supported, the combination of functions supported, a nominal combination of virtual functions to be used by the physical function, and a group identifier for identifying which functions are linked in a combination grouping.

Abstract: A method for communicating with an input/output (I/O) adapter configured to communicate with a locally attached I/O device are provided using cached address translations. With the method, in response to receiving a storage transaction request, a queue element is created in a command queue specifying an untranslated buffer address. The queue element may be retrieved by the I/O adapter and a determination may be made as to whether the queue element contains a read operation command. If so, a translation request may be sent from the I/O adapter to a root complex at substantially a same time as the read operation command is sent to a locally attached external I/O device. The translated address corresponding to the untranslated address of the queue element may be returned and stored in the I/O adapter prior to receiving the data read from the external I/O device.

Abstract: An apparatus and method for communicating with a network adapter using a queue data structure are provided. With the apparatus and method, a device driver invokes device driver services for initializing address translation and protection table (ATPT) entries in a root complex for the queue data structure. The device driver services return untranslated addresses to the device driver which are in turn provided to the network adapter. In response to retrieving a queue element from the queue data structure, the network adapter may request a translation of an untranslated address specified in the queue element and store the translated address in the network adapter prior to receiving a data packet targeting a buffer associated with the queue element.

Abstract: A system and method for communication between host systems using a transaction protocol and shared memories are provided. Shared memories are initialized based on a discovery process in a communication fabric such that at least one endpoint has address ranges in shared memories of at least two host systems. A transaction oriented protocol may be established for using the shared memories of the host systems to communicate between root complexes and endpoints of the same or different host systems. The transaction oriented protocol specifies a series of transactions to be performed by the various elements, e.g., root complex or endpoint, to push or pull data. Various combinations of push and pull transactions may be utilized.

Abstract: A system and method for registering combinations of physical and/or virtual functions for configuring an endpoint are provided. With the system and method, a mechanism informs a management component of a multifunction endpoint's functional combinations. The management component may then use this information to select the functional combinations that are to be made visible to each system image. The informing of the management component may be performed by writing values to various predefined fields in a configuration space for a physical or virtual function that provides information regarding the number of virtual functions supported, the combination of functions supported, a nominal combination of virtual functions to be used by the physical function, and a group identifier for identifying which functions are linked in a combination grouping.

Abstract: A system and method for migration of single root stateless virtual functions are provided. A Single-Root PCI Configuration Manager (SR-PCIM) provides a system image (SI) with possible virtual function (VF) migration scenarios supported by the endpoint (EP). The SR-PCIM may be instructed that a stateless migration of a VF and its associated application(s) from one SI to another is required. Outstanding requests to the VF are completed and any applications associated with the VF are removed from the SI and the VF is detached from its associated physical function (PF). The SWI may then attach the VF to a target PF which may be in the same or a different EP. The SWI makes the VF available to the SI with which the VF is now associated and the SI configures the VF thereby making it available for use by associated applications.