Patents by Inventor Claudia Sgiarovello
Claudia Sgiarovello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10896887Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.Type: GrantFiled: March 7, 2019Date of Patent: January 19, 2021Assignee: Infineon Technologies AGInventors: Marius Aurel Bodea, Terry Richard Heidmann, Marianne Mataln, Claudia Sgiarovello
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Patent number: 10580753Abstract: According to an embodiment of a method of manufacturing a plurality of semiconductor devices on a wafer, the method includes forming a structure layer comprising a plurality of same semiconductor device structures and providing a protective layer on the structure layer. The protective layer on a first one of the plurality of semiconductor device structures differs from the protective layer on a second one of the plurality of semiconductor device structures.Type: GrantFiled: July 21, 2017Date of Patent: March 3, 2020Assignee: Infineon Technologies AGInventors: Martin Mischitz, Harald Huber, Michael Knabl, Claudia Sgiarovello, Caterina Travan, Andrew Wood
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Publication number: 20190348373Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a smaller elastic modulus than the metal layer or layer stack over a temperature range.Type: ApplicationFiled: May 10, 2018Publication date: November 14, 2019Inventors: Marius Aurel Bodea, Terry Richard Heidmann, Marianne Mataln, Claudia Sgiarovello
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Publication number: 20190348382Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.Type: ApplicationFiled: March 7, 2019Publication date: November 14, 2019Inventors: Marius Aurel Bodea, Terry Richard Heidmann, Marianne Mataln, Claudia Sgiarovello
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Patent number: 10340197Abstract: A die includes a plurality of dielectric landings and a conductive material distributed across one or more of the plurality of dielectric landings. Each one of the plurality of dielectric landings electrically separates two conductive landings associated with the one of the plurality of dielectric landings. The conductive material establishes an electrical connection between the two conductive landings associated with the one or more of the plurality of dielectric landings.Type: GrantFiled: June 8, 2017Date of Patent: July 2, 2019Assignee: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
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Patent number: 10269635Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a liquid is provided on a selected portion of the wafer to selectively alter at least one circuit element within the at least one of the plurality of semiconductor device structures.Type: GrantFiled: February 19, 2016Date of Patent: April 23, 2019Assignee: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
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Publication number: 20190027464Abstract: According to an embodiment of a method of manufacturing a plurality of semiconductor devices on a wafer, the method includes forming a structure layer comprising a plurality of same semiconductor device structures and providing a protective layer on the structure layer. The protective layer on a first one of the plurality of semiconductor device structures differs from the protective layer on a second one of the plurality of semiconductor device structures.Type: ApplicationFiled: July 21, 2017Publication date: January 24, 2019Applicant: Infineon Technologies AGInventors: Martin Mischitz, Harald Huber, Michael Knabl, Claudia Sgiarovello, Caterina Travan, Andrew Wood
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Patent number: 9899277Abstract: A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.Type: GrantFiled: February 19, 2016Date of Patent: February 20, 2018Assignee: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
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Patent number: 9786568Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures.Type: GrantFiled: February 19, 2016Date of Patent: October 10, 2017Assignee: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
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Publication number: 20170271216Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures.Type: ApplicationFiled: June 8, 2017Publication date: September 21, 2017Applicant: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
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Publication number: 20170243795Abstract: A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.Type: ApplicationFiled: February 19, 2016Publication date: August 24, 2017Applicant: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
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Publication number: 20170243794Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures.Type: ApplicationFiled: February 19, 2016Publication date: August 24, 2017Applicant: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
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Publication number: 20170243785Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a liquid is provided on a selected portion of the wafer to selectively alter at least one circuit element within the at least one of the plurality of semiconductor device structures.Type: ApplicationFiled: February 19, 2016Publication date: August 24, 2017Applicant: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
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Publication number: 20170242137Abstract: A method for use in manufacturing a plurality of electronic devices from a workpiece. The method includes compiling a set of data records in a data file, wherein each data record represents information uniquely associated with a respective electronic device to be manufactured from the workpiece. Based on the data file, deposition of a substance is controlled at selected locations on the workpiece.Type: ApplicationFiled: February 17, 2017Publication date: August 24, 2017Applicant: Infineon Technologies AGInventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood